Capacitor Electrode Positioning for High Aperture Ratio

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Solution Overview

Problem

In liquid crystal display (LCD) pixel structures, expanding the capacitor electrode to increase capacitance reduces the aperture ratio, leading to increased power consumption due to overlapping with data lines.

Innovation Solution

The capacitor electrode is positioned on the gate insulating layer with a thin capacitor dielectric layer between it and the drain, reducing the capacitor area and avoiding overlap with data lines, thus maintaining a high aperture ratio without increasing loading.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the capacitor electrode area is expanded to increase capacitance, then the storage capacitor capacitance is improved, but the aperture ratio is reduced

Engineering Contradiction:
ImprovecapacitanceVSAvoidaperture ratio
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The capacitor electrode is positioned in the vertical dimension above the gate insulating layer rather than expanding horizontally, utilizing the third dimension to achieve capacitance without sacrificing aperture ratio

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor electrode structure is nested within the existing pixel structure layers, with the capacitor electrode disposed on the gate insulating layer and the capacitor dielectric layer between it and the drain, efficiently using available space

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If the capacitor electrode is located below the data line to increase aperture ratio, then the aperture ratio is improved, but the loading is increased leading to higher power consumption

Engineering Contradiction:
Improveaperture ratioVSAvoidpower consumption
Core Design Contradiction:
Area of stationary objectVSUse of energy by stationary object

Solution Approach 1:

The capacitor electrode is extracted from the data line overlapping region and repositioned above the gate insulating layer, removing the harmful overlap that caused increased loading and power consumption while preserving aperture ratio

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The gate insulating layer serves as an intermediary structure that supports the capacitor electrode, enabling the capacitor to be formed without direct overlap with the data line, thus avoiding increased loading

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design ensures a high aperture ratio while reducing parasitic capacitance and photo current leakage, improving display quality and reducing power consumption.

Implementation Method 1

The capacitor dielectric layer is located between the capacitor electrode and the drain

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The capacitor dielectric layer is located between the capacitor electrode and the drain

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS8456582B2Active device, pixel structure and display panel
Publication Date: 2013.06.04 AU OPTRONICS CORP
  • US8456582B2 patent drawing
  • US8456582B2 patent drawing
  • US8456582B2 patent drawing

AI summary

An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.