Capacitor Electrode Roughness via Doped Silicon Micromasking
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Solution Overview
Problem
The miniaturization of capacitors in microelectronics reduces capacitance due to decreased surface area, and existing methods to increase capacitance, such as using high dielectric constant materials or electrode roughness, face integration challenges, including high heat budgets and nonuniform curvature, which affect reproducibility and reliability.
Innovation Solution
A capacitive device with a stack of layers forming electrodes and an insulator, where a doped silicon region with controlled roughness is used to increase the contact surface between metal electrodes and the dielectric, achieved through anisotropic etching and conformal deposition of metal and dielectric layers, allowing for a high capacitance value with a low heat budget.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If miniaturization of capacitors is implemented to increase integration density, then integration density is improved, but capacitance value deteriorates due to decreased surface area
Solution Approach 1:
The patent transitions from a planar electrode surface to a three-dimensional rough surface structure. By creating hemispherical protrusions on the electrode surface, the effective contact area with the dielectric is increased in the vertical dimension while maintaining the same footprint area, thus increasing capacitance without compromising integration density.
Solution Approach 2:
The patent specifically creates hemispherical protrusions on the electrode surface through controlled oxidation and etching processes. These curved spherical structures provide increased surface area compared to flat planes, directly addressing the capacitance reduction issue while maintaining compact form factor for high integration density.
2Quantity of substance
If high dielectric constant materials are used to maintain capacitance during miniaturization, then capacitance value is improved, but integration difficulty increases
Solution Approach 1:
Instead of changing the dielectric material to high-k materials, the patent changes the geometric parameter of the electrode surface (from flat to rough with hemispherical protrusions). This physical morphology change increases the effective area, allowing the use of standard dielectric materials while achieving the required capacitance values.
3Quantity of substance
If electrode roughness is increased to maintain capacitance during miniaturization, then capacitance value is improved, but heat budget increases
Solution Approach 1:
The patent replaces thermal processing methods (such as high-temperature annealing or sintering used in conventional roughness creation) with a chemical etching process. The electrochemical etching method creates the desired hemispherical surface morphology at lower temperatures, thus maintaining capacitance while reducing the heat budget.
4Area of stationary object
If conventional micromasking methods are used to create electrode roughness, then contact surface is improved, but manufacturing precision deteriorates due to nonuniform curvature
Solution Approach 1:
The patent employs a controlled electrochemical etching process where the formation of hemispherical protrusions is governed by uniform electrochemical reactions. The process parameters (current density, electrolyte composition, etching time) are precisely controlled to ensure uniform nucleation and growth of hemispheres across the entire electrode surface, achieving both increased contact area and uniform curvature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the contact surface between electrodes and dielectric, enhancing capacitance while maintaining a small size and low heat budget, ensuring reproducibility and reliability in microelectronic devices.
Implementation Method 1
achieved through anisotropic etching and conformal deposition of metal and dielectric layers
Implementation Method 2
achieved through anisotropic etching and conformal deposition of metal and dielectric layers
Data Source
AI summary
Capacitive coupling devices and methods of fabricating a capacitive coupling device are disclosed. The coupling device could include a stack of layers forming electrodes and at least one insulator. The insulator could include a region of doped silicon. The silicon could be doped with a species selected from Ce, Cr, Co, Cu, Dy, Er, Eu, Ho, Ir, Li, Lu, Mn, Pr, Rb, Sm, Sr, Tb, Tm, Yb, Y, Ac, Am, Ba, Be, Cd, Gd, Fe, La, Pb, Ni, Ra, Sc, Th, Hf, Tl, Sn, Np, Rh, U, Zn, Ag, and Yb in relief and forming roughnesses relative to the neighboring regions of the same level in the stack. The electrodes and the insulator form conformal layers above the doped silicon region.