Multilayer Capacitor Electrode Segmentation for Deformation Control
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Solution Overview
Problem
Multilayer ceramic capacitors face challenges in achieving high integration density and low equivalent serial inductance due to bar deformation and cutting defects during lamination or compression, as well as uneven size spacing in final chips.
Innovation Solution
A multilayer capacitor design featuring alternately laminated first and second sheets with exposed inner electrodes, a sealing portion made of dielectric slurry or epoxy, and external electrodes on both surfaces to reduce bar deformation and size variation, along with a manufacturing method that includes forming inner electrodes, cutting sheets, laminating, and forming sealing and external terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacitor size is reduced to increase mounting density, then the mounting integration degree is improved, but bar deformation and cutting defects occur during lamination or compression
Solution Approach 1:
The capacitor structure is divided into multiple segments with inner electrodes extending through different layers (first, second, and third lateral surfaces). This segmentation allows stress distribution across multiple points during lamination and compression, reducing bar deformation and cutting defects while maintaining compact size for high mounting density.
Solution Approach 2:
The inner electrodes are configured to extend in multiple spatial dimensions, exposing terminals through first, second, and third lateral surfaces rather than conventional top-bottom orientations. This dimensional change distributes mechanical stress across different planes during compression, preventing deformation while achieving compact footprint for high integration mounting.
2Productivity
If the capacitor size is reduced to increase mounting density, then the mounting integration degree is improved, but uneven spacing between chip sizes occurs
Solution Approach 1:
The sealing portion is applied locally at specific lateral surfaces where inner electrodes are exposed, rather than uniformly across the entire capacitor. This localized sealing approach maintains precise dimensional control and uniform spacing between chips while allowing the compact multi-surface electrode configuration for high mounting density.
3Reliability
If the inner electrode surface area is increased to reduce equivalent serial inductance, then the ESL is reduced, but the capacitor volume increases
Solution Approach 1:
The inner electrodes utilize multiple lateral surfaces (first, second, and third surfaces) for terminal exposure instead of conventional single-plane arrangements. This dimensional configuration increases the effective surface area for electrical connection, reducing equivalent serial inductance while maintaining a compact overall capacitor volume suitable for high-density mounting.
Data Source
AI summary
Disclosed herein is a multilayer capacitor comprising: a laminate in which a plurality of first sheets and second sheets are alternately laminated, wherein the first sheets and the second sheets are disposed in a direction perpendicular to a mounting surface; a first inner electrode formed on the first sheets, wherein the first electrode is exposed through upper, lower, and first lateral surfaces of the laminate; a second inner electrode that is formed on the second sheets and has a horizontally symmetrical shape with respect to the first inner electrode; a sealing portion encapsulating the first and second inner electrodes exposed through two lateral surfaces of the laminate; and an external electrode that is electrically connected to the first and second inner electrodes exposed through the upper and lower surfaces of the laminate.