Capacitor Electrode Segmentation for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In high-density integrated circuit devices, such as DRAM, the non-uniform thickness of dielectric or upper electrode layers can cause leakage current between the upper and lower electrode layers due to the pillar shape of the lower capacitor electrode, which is exacerbated by the presence of cavities and seams in the electrode structure.
Innovation Solution
A method of fabricating an integrated circuit device involves forming a mold layer with a hole and creating a first lower capacitor electrode pattern with a hollow cylindrical shape and an opening, followed by a second lower capacitor electrode pattern that plugs the opening, both made of titanium nitride and formed using CVD or ALD processes at temperatures below 500°C, to create a structure with a void and a planar upper surface, which reduces leakage current by encapsulating the seam and ensuring uniform coverage with a dielectric layer and upper electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pillar shape lower capacitor electrode is used for high-density integration, then device density is improved, but leakage current increases due to non-uniform dielectric layer thickness
Solution Approach 1:
The lower capacitor electrode is segmented into multiple patterns (first and second lower capacitor electrode patterns) arranged in an interlaced configuration. This segmentation creates a more uniform overall electrode structure that reduces localized stress concentrations and prevents seam formation, thereby reducing leakage current while maintaining high device density.
Solution Approach 2:
The dielectric layer thickness is optimized locally by forming it conformally on the interlaced electrode patterns. This local quality approach ensures uniform dielectric coverage in critical areas where seams would otherwise form, preventing leakage pathways while maintaining the high-density pillar structure.
2Productivity
If a pillar shape lower capacitor electrode is used, then device density is improved, but manufacturing precision deteriorates due to non-uniform dielectric and electrode layer deposition
Solution Approach 1:
Dividing the lower capacitor electrode into multiple interlaced patterns creates a more uniform topography that enables precise conformal deposition of subsequent dielectric and electrode layers, improving manufacturing precision while maintaining high device density.
Solution Approach 2:
The interlaced arrangement of electrode patterns in the planar dimension creates a more uniform three-dimensional structure for layer deposition, transforming the deposition challenge from a vertical height variation problem to a more manageable conformal coating problem.
3Device complexity
If cavities and seams are present in the electrode structure, then device complexity is reduced, but reliability deteriorates due to increased leakage current
Solution Approach 1:
The electrode is segmented into interlaced patterns that eliminate continuous seams while maintaining structural simplicity. This segmentation prevents leakage pathways without requiring complex additional components or processing steps.
Solution Approach 2:
The segmentation of the electrode into interlaced patterns converts what would be harmful continuous seams into beneficial discontinuous structures. The gaps between interlaced patterns prevent leakage current while the overall structure remains relatively simple to manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current by encapsulating the seam and ensuring uniform coverage, enhancing the reliability and performance of high-density integrated circuit devices by maintaining a low contact resistance and preventing seam exposure during subsequent processes.
Implementation Method 1
forming the first lower capacitor electrode pattern and the second lower capacitor electrode pattern using a CVD or ALD process
Implementation Method 2
forming the first lower capacitor electrode pattern and the second lower capacitor electrode pattern using a CVD or ALD process
Data Source
AI summary
An integrated circuit device with capacitors and methods of forming the integrated circuit device are provided. The methods may include forming a first lower capacitor electrode pattern on an inner surface of a hole in a mold layer. The first lower capacitor electrode pattern may have a hollow cylindrical shape and an opening in an upper surface. The method may further include forming a second lower capacitor electrode pattern plugging the opening and an upper surface of the second lower capacitor electrode pattern may be planar. The first and the second lower capacitor electrode patterns may comprise a lower capacitor electrode including a void. Additionally, the method may include removing the mold layer to expose the lower capacitor electrode, forming a dielectric layer on the lower capacitor electrode, and forming an upper capacitor electrode layer on the dielectric layer.