Capacitor Electrode Structure for Semiconductor Miniaturization
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Solution Overview
Problem
In the semiconductor industry, capacitors and other devices on a substrate lead to increased layout area and thickness due to the need for interconnect structures above them, limiting miniaturization efforts.
Innovation Solution
A semiconductor structure where the upper electrode of a capacitor covers both the top surface and sidewall of the lower electrode, with an insulating layer in between, and pads connected to the interconnect structure, allowing for reduced thickness and layout area by utilizing the uppermost metal layer as the lower electrode and pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitors and semiconductor devices are disposed on a substrate with interconnect structures above them, then the layout area is reduced, but the thickness of the semiconductor device is increased
Solution Approach 1:
The upper electrode is disposed to cover the top surface and sidewall of the lower electrode, creating a nested configuration where one electrode structure contains another. This nesting approach increases capacitance within a compact vertical footprint, addressing the contradiction by maximizing space utilization without proportionally increasing thickness.
Solution Approach 2:
The electrode structure transitions from a planar two-dimensional arrangement to a three-dimensional configuration where the upper electrode wraps around the lower electrode's sidewall. This dimensional change enables increased capacitance density by utilizing vertical and lateral spaces more effectively, reducing the required layout area while controlling thickness growth.
2Reliability
If the upper electrode covers the top surface and sidewall of the lower electrode, then the capacitance is enhanced, but the manufacturing complexity is increased
Solution Approach 1:
The formation of the upper electrode is merged with the formation of the second conductive layer that will become the pads. By combining these two electrode formation steps into a single continuous process using the same conformal deposition and patterning sequence, the manufacturing complexity is minimized while achieving the enhanced capacitance structure.
Solution Approach 2:
The lower electrode (first conductive layer) is formed and patterned in advance before the upper electrode is deposited. This preliminary action establishes the foundation structure, allowing the upper electrode to be conformally deposited over it in a subsequent step, simplifying the overall manufacturing process while achieving the nested electrode configuration.
3Adaptability or versatility
If the second conductive material layer covers the top surface and sidewall of the capacitor, then the pads can be extended onto the capacitor, but the process steps are increased
Solution Approach 1:
The formation of the pads and the upper electrode are merged into a single process step. The second conductive material layer is deposited conformally to cover both the capacitor structure and the pad regions, then patterned in one operation to define both the upper electrode and the pads simultaneously, reducing the total number of process steps.
Solution Approach 2:
The second conductive material layer serves multiple functions: it forms the upper electrode of the capacitor, creates the pads for external connections, and provides electrical interconnection between them. This multi-functionality approach consolidates what could be separate structures into a single integrated layer, improving adaptability while minimizing process complexity.
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a semiconductor device, an interconnect structure, a capacitor, and a plurality of pads. The semiconductor device is disposed at the substrate. The interconnect structure is disposed on the substrate and electrically connected to the semiconductor device. The capacitor is disposed on the interconnect structure and electrically connected to the interconnect structure. The capacitor includes a first electrode, a second electrode covering a top surface and a sidewall of the first electrode, and an insulating layer disposed between the first electrode and the second electrode. The plurality of pads are disposed on the interconnect structure and electrically connected to the interconnect structure, wherein at least one of the plurality of pads is electrically connected to the capacitor.