Integrated Capacitor Element Layout for Low-ESR High-Density Arrays
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Solution Overview
Problem
Existing capacitor array technologies face challenges in forming cathode and anode regions, leading to increased manufacturing complexity and reduced volumetric capacitance density, particularly when connecting multiple capacitor elements in an array structure.
Innovation Solution
A capacitor element design featuring a cathode region with a porous valve metal portion and a dielectric layer, along with a cathode layer including a solid-electrolyte layer, and an anode region that separates adjacent cathode regions, allowing for easier formation and integration of these regions without the need for complex connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple capacitor elements are connected in an array structure, then low ESR and low ESL with good radio frequency characteristics are achieved, but manufacturing process complexity increases and volumetric capacitance density decreases
Solution Approach 1:
The patent merges multiple capacitor elements into a single integrated capacitor element structure. The anode plate, porous portion, dielectric layer, and cathode layer are formed as one unified component rather than connecting separate elements, thereby achieving low ESR and low ESL while simplifying the manufacturing process and increasing volumetric capacitance density.
Solution Approach 2:
The patent transitions from a two-dimensional array connection approach to a three-dimensional integrated structure. By forming the porous portion and dielectric layer in vertical stacking within a single element, the design achieves array-like electrical characteristics without the manufacturing complexity of planar arrays.
2Reliability
If multiple capacitor elements are connected in an array structure, then low ESR and low ESL with good radio frequency characteristics are achieved, but volumetric capacitance density decreases
Solution Approach 1:
The patent implements a nested structure where the porous portion is formed within the anode plate, the dielectric layer is formed on the porous portion, and the cathode layer is formed on the dielectric layer. This nested arrangement maximizes the use of internal space, achieving high volumetric capacitance density while maintaining the electrical characteristics of an array structure.
Solution Approach 2:
The patent utilizes a porous portion composed of valve metal that provides high surface area within a compact volume. The porous structure enables increased capacitance density by providing extensive surface area for dielectric layer formation without increasing the overall volume of the capacitor element.
3Ease of manufacture
If cathode region and anode region are formed in a single capacitor element, then manufacturing is simplified, but region formation difficulty arises
Solution Approach 1:
The patent segments the capacitor element into distinct functional regions: an anode region with the anode plate and porous portion, and a cathode region with the dielectric layer and cathode layer. This segmentation is achieved through selective formation processes where the porous portion is formed only in the cathode region, clearly defining region boundaries while simplifying manufacturing.
Solution Approach 2:
The patent applies local quality by forming the porous portion only in specific regions (cathode region) and not in others (anode region). This localized formation approach allows clear differentiation between cathode and anode regions within a single element, simplifying the overall manufacturing process while maintaining proper region separation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design simplifies the formation of cathode and anode regions, enhancing manufacturing efficiency and maintaining high volumetric capacitance density by ensuring clear separation and integration of cathode and anode areas within the capacitor element.
Implementation Method 1
a porous portion composed of a valve metal in the cathode region and not in the anode region
Implementation Method 2
a dielectric layer on a surface of the porous portion in the cathode region
Implementation Method 3
a cathode layer on a surface of the dielectric layer in the cathode region, the cathode layer including a solid-electrolyte layer
Data Source
AI summary
A capacitor element having a cathode region and an anode region in a plan view thereof, the capacitor element including: an anode plate in at least the anode region; a porous portion composed of a valve metal in the cathode region and not in the anode region; a dielectric layer on a surface of the porous portion in the cathode region; and a cathode layer on a surface of the dielectric layer in the cathode region, the cathode layer including a solid-electrolyte layer.