Capacitor-Enhanced Comparator for Switched-Capacitor Circuits
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Solution Overview
Problem
Comparators in data communication systems face challenges with kickback noise due to unstable input common-mode voltages, leading to performance degradation and increased sensitivity to kickback effects.
Innovation Solution
A circuit configuration is introduced, featuring capacitors coupled to the comparator inputs to stabilize the common-mode voltage and reduce kickback noise, which includes a first and second capacitor from the clock signal to the differential paths and additional capacitors from the common mode voltage, allowing direct connection of switched-capacitor networks to the comparator without an active preamplifier, thereby minimizing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If an active preamplifier is used to stabilize comparator input common-mode voltage, then the common-mode stability is improved, but the power consumption and circuit area increase
Solution Approach 1:
The patent removes the active preamplifier component from the circuit while maintaining common-mode stability through alternative means (switched-capacitor networks and clock signal coupling), thereby eliminating the power consumption and area overhead associated with the preamplifier
Solution Approach 2:
The patent introduces capacitors coupled to the clock signal as an intermediary mechanism to stabilize the common-mode voltage at the comparator inputs, replacing the need for an active preamplifier while achieving the same stabilizing effect
2Stability of the object's composition
If an active preamplifier is used to stabilize comparator input common-mode voltage, then the common-mode stability is improved, but the circuit area increases
Solution Approach 1:
The patent removes the active preamplifier component from the circuit while maintaining common-mode stability through alternative means (switched-capacitor networks and clock signal coupling), thereby eliminating the area overhead associated with the preamplifier
Solution Approach 2:
The patent uses simple capacitors and switched-capacitor networks instead of complex active preamplifier circuits, achieving the same function with much smaller, simpler components that occupy less area
3Device complexity
If traditional comparator configuration is used without capacitive compensation, then the circuit complexity is reduced, but the kickback noise sensitivity increases
Solution Approach 1:
The patent introduces capacitors coupled to the clock signal as an intermediary mechanism to filter and stabilize the common-mode voltage, reducing kickback noise sensitivity without significantly increasing circuit complexity
Solution Approach 2:
The patent modifies the electrical parameters at the comparator inputs by introducing capacitive elements that change the voltage stability and noise characteristics, reducing kickback effects while maintaining circuit simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains stable comparator input common-mode voltages, reduces sensitivity to kickback effects, and enables faster response times while eliminating the need for an active preamplifier, resulting in improved performance and reduced power consumption.
Implementation Method 1
A first capacitor (Cc1) is coupled from the clock signal to the first differential signal path. A second capacitor (Cc2) is coupled from the clock signal to the second differential signal path.
Implementation Method 2
Some embodiments may provide a capacitive path to compensate for the kickback voltage in an opposite direction to the kickback voltage by introducing a first capacitor Cc1 and a second capacitor Cc2.
Data Source
AI summary
Apparatus and associated methods relate to a circuit that is configured to keep a comparator input voltage stable. In an illustrative example, the circuit may include a first differential path coupled to a first switched-capacitor network's output, a second differential path coupled to a second switched-capacitor network's output. A comparator may have a first input coupled to the first differential path and a second input coupled to the second differential path. The comparator may be controlled by a clock signal to perform comparison. A first capacitor may be coupled from the clock signal to the first differential signal path and a second capacitor may be coupled from the clock signal to the second differential signal path. By introducing the first capacitor and the second capacitor, the comparator input common-mode may keep stable, and the comparator may be less sensitive to kickback effects.