Capacitor ESD Protection via Transistor Control Circuit

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Solution Overview

Problem

Capacitors in integrated circuits are vulnerable to electrostatic discharge (ESD) due to direct coupling of transistor gates to power rails, leading to potential transistor breakdown and increased leakage current, especially in power saving modes.

Innovation Solution

A capacitor design incorporating a first and second transistor, along with a control circuit that couples their control terminals indirectly to the capacitor terminals, allowing the control circuit to turn off the transistors during power saving modes to reduce leakage current and enhance ESD protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the control terminal of the transistor is directly coupled to the power rail, then the transistor can be controlled to function as a capacitor, but the transistor becomes vulnerable to ESD damage and breakdown

Engineering Contradiction:
ImproveESD protection capabilityVSAvoidcapacitor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a control circuit as an intermediary between the power rail and the control terminal of the transistor. This control circuit includes additional transistors and coupling elements that indirectly connect the power rail to the capacitor's control terminal, preventing direct ESD exposure while maintaining capacitive functionality. The intermediary structure isolates the main transistor's control terminal from direct ESD strikes on the power rail.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the transistor remains on continuously to maintain capacitor function, then the capacitor is always available, but leakage current increases during power saving modes

Engineering Contradiction:
Improvecapacitor availabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements dynamic control of the transistor states based on operational modes. The control circuit dynamically adjusts the on/off states of the transistors according to whether the system is in normal mode or power-saving mode. During power-saving modes, the control circuit turns off the transistors to minimize leakage current, while during normal operation, it activates them to provide capacitive functionality, thus adapting the system's behavior to current operational requirements.

Inventive Principle:
Principle #15Dynamics

3Reliability

If additional transistors and control circuits are added to protect against ESD and reduce leakage, then ESD protection and leakage reduction are improved, but the device complexity increases

Engineering Contradiction:
Improvetransistor protectionVSAvoidcapacitor circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control circuit components, including the additional transistors and coupling elements, serve multiple functions simultaneously: they provide ESD protection by isolating the main transistor's control terminal, enable dynamic power management by controlling transistor on/off states, and maintain the capacitive function when activated. This multi-functionality reduces the need for separate dedicated protection circuits, thereby limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10892260B2Capacitor
Publication Date: 2021.01.12 HIMAX TECH LTD
  • US10892260B2 patent drawing
  • US10892260B2 patent drawing
  • US10892260B2 patent drawing

AI summary

A capacitor includes a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor is coupled to the first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. In a normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor through the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor through the control circuit. In a power saving mode, the control circuit turns off the first transistor and the second transistor.