Capacitor-Free DRAM With Floating Gate And Transition Layer
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Solution Overview
Problem
Conventional DRAM devices face limitations in retention characteristics, process complexity, and manufacturing cost due to the use of capacitors and floating bodies, which hinder their miniaturization and compatibility with CMOS processes on bulk wafers.
Innovation Solution
A DRAM device structure is proposed with a modified upper gate region, eliminating the need for capacitors and floating bodies, featuring a channel region, gate insulating film, floating gate, transition layer, and control gate, where the control gate generates a potential difference to store or release charges, reducing chip size and process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in conventional 1T-1C DRAM to store charges, then retention characteristics are improved, but cell area increases and manufacturing complexity increases
Solution Approach 1:
The patent extracts and removes the capacitor component from the conventional 1T-1C DRAM structure, replacing it with a capacitor-free 1T DRAM design that uses a floating body to store charges, thereby reducing cell area while maintaining retention characteristics
Solution Approach 2:
The patent changes the physical parameters of the transistor by introducing a floating body structure with specific doping concentrations and dimensions, enabling charge storage functionality previously provided by capacitors, thus reducing cell area without sacrificing retention
2Reliability
If a capacitor is used in conventional 1T-1C DRAM to store charges, then retention characteristics are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the capacitor component from the conventional 1T-1C DRAM structure, replacing it with a capacitor-free 1T DRAM design that uses a floating body to store charges, thereby reducing cell area while maintaining retention characteristics
Solution Approach 2:
The patent merges the charge storage function into the transistor's floating body structure, combining what were previously separate components (transistor + capacitor) into a single integrated structure, simplifying device complexity and manufacturing
3Area of stationary object
If 1T-DRAM with floating body is used to reduce cell area, then cell area is reduced, but production cost increases due to SOI wafer requirements
Solution Approach 1:
The patent changes the substrate parameter from SOI (silicon-on-insulator) to bulk silicon, modifying the floating body formation method to be compatible with standard CMOS processes on bulk wafers, thereby reducing production cost while maintaining the compact cell area
4Area of stationary object
If 1T-DRAM with floating body is used to reduce cell area, then cell area is reduced, but channel level stability deteriorates due to floating body nature
Solution Approach 1:
The patent applies local quality control by introducing specific doping regions and structures around the floating body, such as lightly-doped drain regions and isolation structures, to stabilize the channel level locally without increasing overall cell area
5Ease of manufacture
If conventional 1T-1C DRAM is used to maintain stability, then manufacturing compatibility is good, but retention characteristics and sensing window are limited
Solution Approach 1:
The patent changes the device structure parameters by eliminating the capacitor and using a floating body transistor, enabling long retention characteristics and large sensing window while maintaining compatibility with standard CMOS fabrication processes through careful process integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves long retention characteristics, reduces manufacturing costs, and enhances compatibility with conventional processes, enabling a large sensing window while overcoming the limitations of traditional 1T-1C and 1T-DRAM devices.
Implementation Method 1
a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference
Data Source
AI summary
Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.