Capacitor-Free Memory Cell Layout for Higher Density DRAM
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Solution Overview
Problem
The conventional 1T1C architecture in dynamic random access memory (DRAM) faces challenges in reducing circuit area as capacitance occupies a significant portion, especially in three-dimensional stacked structures, increasing production costs.
Innovation Solution
A memory structure comprising first and second transistors arranged in arrays, with word and bit lines extended along the normal direction of a substrate, eliminating the need for storage capacitance and reducing circuit layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the conventional 1T1C architecture is used in three-dimensional stacked structure, then the memory capacity can be increased, but the capacitance occupies a large amount of circuit area which increases production cost
Solution Approach 1:
The patent extracts and eliminates the storage capacitance component from the memory cell architecture. By using the gate of the second transistor as the data storage node instead of a dedicated capacitance, the design removes the need for separate capacitance structures, thereby reducing circuit area while maintaining memory functionality
Solution Approach 2:
The gate of the second transistor serves multiple functions: it acts as both the control gate for the transistor and the data storage node. This multi-functionality eliminates the need for dedicated capacitance structures, reducing the overall circuit area while preserving the memory storage capability
2Length of moving object
If the circuit size of the memory cell is adjusted in conventional 1T1C architecture, then the memory dimension decreases, but the proportion of the area of the capacitance increases significantly
Solution Approach 1:
The patent extracts the storage function from the dedicated capacitance and relocates it to the transistor gate. This eliminates the need for separate capacitance structures, ensuring that as memory dimensions decrease, the capacitance area proportion does not increase
3Reliability
If conventional 1T1C architecture is used, then the memory cell can store data, but the complexity of the process when forming the capacitance causes great obstacles
Solution Approach 1:
The patent removes the capacitance formation process from the manufacturing sequence by using the transistor gate as the storage node. This extraction of the capacitance component eliminates the complex capacitance formation steps while preserving the data storage capability through the gate's inherent electrical characteristics
Solution Approach 2:
The patent merges the gate structure with the storage node function. By combining these two elements into a single structure, the design eliminates the need for separate capacitance formation processes, thereby simplifying the manufacturing process while maintaining data storage reliability
Data Source
AI summary
A memory structure includes a plurality of first transistors and a plurality of second transistors. The first transistors are arranged in a first array. First ends of the first transistors are respectively coupled to a plurality of first bit lines, and gates of the first transistors are respectively coupled a plurality of first word lines. The second transistors are arranged in a second array. Gates of the second transistors are respectively coupled to second ends of the first transistors, and second ends and first ends of the second transistors are respectively coupled to second bit lines and second word lines. The first transistors and the second transistors are disposed on a substrate. The first word lines or the first bit lines are extended along a normal direction of a plane of the substrate, and the second word lines or the second bit lines are extended along the normal direction.