Capacitor Geometry Adjustment for Foundry Process Variation
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Solution Overview
Problem
The process parameters used in small-scale engineering foundries and production foundries for fabricating capacitors often differ, leading to variations in capacitance values, which require manual redesign of capacitor layouts to match specifications, increasing manufacturing costs and altering die area consumption.
Innovation Solution
A method to adjust the geometry of capacitors by trimming conductive fingers to match capacitance values without changing the die area, allowing for automatic adjustments in layout design data files during the tape-out process, thereby avoiding manual redesign and data regeneration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the capacitor layout is manually redesigned to adjust capacitance value, then the capacitance value can be matched between foundries, but the die area consumed by the capacitor changes and manufacturing cost increases
Solution Approach 1:
The patent adjusts the capacitance value by changing geometric parameters of the capacitor structure, specifically the width of conductive fingers or plates, while maintaining the overall die area constant. This allows capacitance tuning through parameter modification rather than layout redesign, resolving the contradiction between achieving precise capacitance matching and maintaining original die area consumption.
2Manufacturing precision
If the capacitor layout is manually redesigned to adjust capacitance value, then the capacitance value can be matched between foundries, but manufacturing cost increases due to data file regeneration
Solution Approach 1:
The patent establishes a pre-defined relationship between geometric parameters and capacitance values, allowing automatic adjustment of capacitor dimensions based on foundry-specific process parameters. This preliminary setup enables automated compensation for foundry variations without manual intervention, thereby reducing manufacturing costs by eliminating the need for manual layout redesign and data file regeneration.
Solution Approach 2:
By modifying geometric parameters such as conductive finger width or plate dimensions, the patent achieves capacitance adjustment through automated parameter scaling rather than manual layout redesign. This approach maintains ease of manufacture by avoiding costly regeneration of GDS data files and manual engineering efforts.
3Adaptability or versatility
If process parameters differ between foundries, then capacitance value varies, but manual redesign is required to compensate
Solution Approach 1:
The patent compensates for foundry process parameter variations by automatically adjusting geometric parameters of the capacitor structure. Instead of requiring complex manual layout redesign, the system uses parameter scaling based on dielectric constant ratios between foundries, thereby maintaining adaptability to different foundries while reducing device complexity and design effort.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables capacitance value adjustments without affecting the die area, reducing manufacturing costs and maintaining the original die area consumption, while ensuring consistent capacitance across different foundries.
Implementation Method 1
a first capacitor value when fabricated in a first foundry using a first set of process parameters
Implementation Method 2
a process parameter, such as a dielectric constant value of a dielectric material, can be higher in a production foundry
Data Source
AI summary
According to one exemplary embodiment, a method for adjusting geometry of a capacitor includes fabricating a first composite capacitor residing in a first standard cell with a first set of process parameters. The method further includes using a second standard cell having substantially same dimensions as the first standard cell. The method further includes using a capacitance value from the first composite capacitor to adjust a geometry of a second composite capacitor residing in the second standard cell, wherein the second composite capacitor is fabricated with a second set of process parameters. The geometry of the second composite capacitor can be adjusted to cause the second composite capacitor to have a capacitance value substantially equal to the capacitance value from the first composite capacitor.