Semiconductor Capacitor Hole Patterning to Avoid SADP Loading Effects
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Solution Overview
Problem
The Self-Aligned Double Patterning (SADP) process in semiconductor manufacturing often results in inconsistent capacitor sizes and heights due to the loading effect during etching, leading to reduced yield and storage capacity in dynamic random access memory (DRAM) devices.
Innovation Solution
A method involving the formation of discrete first and second mask layers, sidewall layers, and repair layers to define consistent via positions and etching rates, ensuring precise capacitor hole formation by etching along the vias, which avoids the loading effect and tip discharge issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SADP process is used to form capacitors, then capacitor pattern definition is achieved, but loading effect during etching causes inconsistent capacitor sizes and heights
Solution Approach 1:
The patent divides the etching process into multiple independent etching operations, each targeting specific regions defined by different mask layers. This segmentation allows each etching step to proceed without loading effects from other regions, ensuring consistent etching rates and uniform capacitor dimensions across the substrate.
Solution Approach 2:
The patent forms multiple mask layers with precisely defined patterns before the etching process. These pre-formed masks serve as protective barriers that prevent etching in unwanted areas, ensuring that only the intended capacitor regions are etched. This preliminary patterning eliminates loading effects that would otherwise occur during simultaneous multi-region etching.
2Manufacturing precision
If two-layer mask pattern is used in SADP, then capacitor hole pattern is defined, but different capacitor heights and insufficient etching occur
Solution Approach 1:
The patent applies different mask patterns to different local regions of the substrate, with each mask layer defining specific capacitor arrays. This local differentiation allows precise control over etching in each region, ensuring uniform capacitor heights while managing process complexity through regional specialization rather than universal masking.
Solution Approach 2:
The patent transitions from planar mask patterns to three-dimensional mask structures with varying thicknesses and positions. This dimensional enhancement allows the masks to serve multiple functions simultaneously - defining patterns, controlling etching depth, and preventing loading effects - thereby achieving uniform capacitor heights without proportionally increasing process complexity.
3Manufacturing precision
If SADP etching is performed, then capacitor holes are formed, but tip discharge and electrical failures occur
Solution Approach 1:
The patent extracts and removes the problematic chamfered corners from the via structures by using masks with rounded or rounded-corner patterns. This extraction eliminates the geometric features that concentrate electric fields and cause tip discharge, thereby preventing electrical failures while maintaining high-quality capacitor hole formation.
Solution Approach 2:
The patent converts the potential harm of sharp corners causing tip discharge into a benefit by deliberately designing mask patterns with rounded corners. This design choice eliminates electric field concentration and prevents discharge, while the rounded mask patterns themselves become the beneficial feature that ensures reliable capacitor formation without electrical failures.
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: providing a base; forming multiple discrete first mask layers on the base; forming multiple sidewall layers, in which each sidewall layer is configured to encircle one of the first mask layers, and each sidewall layer is connected to closest sidewall layers, the side walls, away from the first mask layers, of multiple connected sidewall layers define initial first vias and each of the initial first vias is provided with chamfers; removing the first mask layers, and each sidewall layer defines a second via; after removing the first mask layers, forming repair layers which are located on the side walls, away from the second vias, of the sidewall layers and fill the chamfers of the initial first vias to form first vias; and etching the base along the first vias and the second vias to form capacitor holes on the base.