Multilayer Chip Capacitor Impedance Control via Electrode Segmentation
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Solution Overview
Problem
Multilayer chip capacitors face challenges in maintaining uniform impedance characteristics across a wide frequency band due to excessive low equivalent series resistance (ESR) and high equivalent series inductance (ESL), which affects the stability of power supply circuits, especially in micro processing units (MPUs) with increasing integration density and operating frequency.
Innovation Solution
A multilayer chip capacitor design with a lamination structure featuring a first and second capacitor part, connected via connection conductor lines that adjust ESR and ESL, ensuring a low ESL and suitable ESR, achieved by varying the number and arrangement of inner electrodes, outer electrodes, and using conductive lines as resistors to control impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the equivalent series resistance (ESR) is reduced to improve high frequency impedance, then the high frequency impedance is reduced, but the stability of power supply circuit deteriorates due to power network resonance
Solution Approach 1:
The patent applies parameter changes by carefully controlling the ESR within a specific range (0.01Ω to 0.1Ω) rather than simply minimizing it. This parameter optimization resolves the contradiction by finding the optimal balance point where high frequency impedance is sufficiently reduced while maintaining circuit stability against power network resonance.
Solution Approach 2:
The patent applies local quality by using different electrode material compositions in different regions of the capacitor. The outer electrodes and inner electrodes have different resistance characteristics, with the outer electrodes having higher resistance to maintain stability while inner electrodes provide low impedance pathways. This spatial differentiation of electrical properties resolves the contradiction between low impedance and stability.
2Ease of manufacture
If conventional electrode arrangements are used, then manufacturing is simple, but the impedance magnitude cannot be maintained to be low and uniform within broadband frequency range
Solution Approach 1:
The patent applies segmentation by dividing the capacitor into multiple electrode pairs (first inner electrode with first outer electrode, second inner electrode with second outer electrode) arranged in a specific pattern. This segmentation creates multiple parallel current paths that reduce overall ESL while maintaining manufacturability through standardized layering processes.
Solution Approach 2:
The patent applies asymmetry by positioning the inner electrodes and outer electrodes in a non-symmetric interdigitated arrangement. The first and second inner electrodes are disposed at different positions relative to the outer electrodes, creating unequal but complementary current paths that collectively reduce ESL and broaden the frequency range over which low impedance is maintained.
3Quantity of substance
If high-resistance materials are used for electrodes to increase ESR, then ESR characteristics improve, but localized heat spots occur due to current concentration at pinholes
Solution Approach 1:
The patent applies local quality by using high-resistance materials selectively in specific electrode regions rather than uniformly throughout. The outer electrodes incorporate high-resistance material to achieve desired ESR characteristics, while the inner electrodes use low-resistance materials to provide robust current pathways that distribute current density and prevent localized heating at pinhole defects.
Solution Approach 2:
The patent applies composite materials by combining different electrode materials with contrasting resistance properties. The electrode structure comprises a composite of high-resistance outer electrodes and low-resistance inner electrodes, creating a multi-material system that simultaneously achieves target ESR values while distributing current flow to avoid concentration effects that cause localized heat spots.
Data Source
AI summary
A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.