Capacitor Interface Stack for Low-Leakage Semiconductor Memory
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Solution Overview
Problem
As semiconductor devices undergo increased integration, the narrow distances between patterns lead to challenges in capacitor design, particularly in reducing capacitor leakage and enhancing sensing margins due to increased aspect ratios of storage nodes, where existing technologies struggle to effectively manage the interface between electrodes and dielectric layers.
Innovation Solution
The implementation of a semiconductor device with a lower electrode, a silicon nitride-based supporter, a dielectric layer, and interfacial layers comprising metal oxides and nitrides, such as niobium oxide and niobium nitride, which are selectively formed to reduce trap sites and enhance the dielectric constant, thereby improving capacitance and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the aspect ratio of the storage node is increased to reduce the area occupied by the capacitor, then the integration density is improved, but the capacitor leakage increases and the sensing margin decreases
Solution Approach 1:
An interfacial layer comprising a metal oxide layer and a metal nitride layer is introduced between the lower electrode and the dielectric layer. This interfacial layer acts as an intermediary that reduces trap sites at the interface, thereby decreasing capacitor leakage and improving sensing margin while allowing the storage node to maintain its high aspect ratio for compact integration.
Solution Approach 2:
The interfacial layer is formed as a composite structure with a metal oxide layer (such as niobium oxide, titanium oxide, or tantalum oxide) and a metal nitride layer (such as niobium nitride, titanium nitride, or tantalum nitride). This composite material structure combines the benefits of both materials: the metal oxide provides good interface adhesion and the metal nitride provides low resistance and trap site reduction, together resolving the contradiction between compact size and reliability.
2Stability of the object's composition
If a supporter is added to support the outer wall of the lower electrode to maintain structural integrity at high aspect ratios, then the structural stability is improved, but the device complexity increases
Solution Approach 1:
A thin film supporter is used to support the outer wall of the lower electrode. The supporter is formed as a thin film structure that provides necessary mechanical support to maintain the structural integrity of the high aspect ratio lower electrode, while its thin film nature minimizes the increase in device complexity and occupies minimal space.
3Reliability
If interfacial layers are selectively formed on the lower electrode surface to reduce trap sites, then the capacitor leakage is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The interfacial layer is selectively formed only on the surface of the lower electrode where it contacts the dielectric layer, rather than uniformly across all surfaces. This selective formation is achieved through precise masking and deposition techniques that target only the specific interface region, reducing trap sites and capacitor leakage while managing manufacturing precision requirements through localized processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces capacitor leakage, enhances the sensing margin, and increases the dielectric constant, leading to improved capacitance and leakage current characteristics, particularly in high-frequency regions.
Implementation Method 1
interfacial layers comprising metal oxides and nitrides, such as niobium oxide and niobium nitride, which are selectively formed to reduce trap sites
Implementation Method 2
enhance the dielectric constant, thereby improving capacitance
Data Source
AI summary
A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.


