Semiconductor Capacitor Interfacial Layers for Low Leakage
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Solution Overview
Problem
As semiconductor devices undergo increased integration, the narrow distances between patterns lead to challenges in forming capacitors with high aspect ratios, resulting in issues such as capacitor leakage and reduced capacitance due to increased trap sites and dielectric relaxation characteristics.
Innovation Solution
The introduction of interfacial layers composed of metal oxides and nitrides between the lower electrode and dielectric layer, and between the dielectric layer and the upper electrode, which are formed through specific pre-treatment and post-treatment processes using gases like H2, D2, NH3, and plasma, to enhance the dielectric constant and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of the storage node is increased to maintain capacitance in high-density memory devices, then the storage capacitance is improved, but capacitor leakage increases and trap sites increase due to dielectric relaxation characteristics
Solution Approach 1:
An interfacial layer is introduced between the lower electrode and the dielectric layer to act as an intermediary. This interfacial layer includes a first interfacial layer selectively formed on the lower electrode and a second interfacial layer between the dielectric layer and the upper electrode, which prevents direct contact between the electrode and dielectric, thereby reducing leakage current and trap sites while maintaining storage capacitance.
2Quantity of substance
If the aspect ratio of the storage node is increased to maintain capacitance in high-density memory devices, then the storage capacitance is improved, but the number of trap sites increases due to dielectric relaxation characteristics
Solution Approach 1:
The interfacial layer serves as a mediator that reduces the formation of trap sites at the electrode-dielectric interface. By introducing this intermediate layer with specific material composition (including metal oxides and nitrides), the direct interface between electrode and dielectric is eliminated, reducing dielectric relaxation effects and trap site formation while preserving the required storage capacitance.
3Reliability
If interfacial layers are added between electrode and dielectric layer, then leakage current is reduced and sensing margin is improved, but device complexity increases
Solution Approach 1:
The interfacial layer is selectively formed only at critical interfaces where electrode meets dielectric, rather than uniformly throughout the device. The first interfacial layer is selectively formed on the lower electrode surface, and the second interfacial layer is formed only where needed between the dielectric and upper electrode, maintaining local quality improvement without excessive overall complexity.
Solution Approach 2:
The interfacial layer is divided into multiple segments: a first interfacial layer at the lower electrode interface and a second interfacial layer at the upper electrode interface. This segmentation allows each layer to be optimized for its specific function and formed using targeted processes, reducing overall complexity compared to a single thick interfacial layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves the sensing margin and capacitance of capacitors by reducing trap sites and leakage current, while promoting a tetragonal crystalline phase in the dielectric layer, thereby enhancing the dielectric relaxation characteristics.
Implementation Method 1
performing a pre-treatment to form an adsorption inhibitor on a surface of the supporter
Implementation Method 2
exposing the metal oxide to a post-treatment to form the metal nitride. The post-treatment uses H2, D2, or NH3 directly or simultaneously with plasma
Implementation Method 3
The pre-treatment uses H2, D2, NH3, H2O, O3, O2, or H2O2 directly or simultaneously with plasma
Implementation Method 4
a dielectric layer including a tetragonal crystalline hafnium oxide
Data Source
AI summary
A semiconductor device includes a lower electrode; a supporter supporting an outer wall of the lower electrode; a dielectric layer formed on the lower electrode and the supporter; an upper electrode on the dielectric layer; a first interfacial layer disposed between the lower electrode and the dielectric layer and selectively formed on a surface of the lower electrode among the lower electrode and the supporter; and a second interfacial layer disposed between the dielectric layer and the upper electrode, wherein the first interfacial layer is a stack of a metal oxide contacting the lower electrode and a metal nitride contacting the dielectric layer.