Capacitor Interposer Layer for 3DIC Voltage Droop Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-dimensional integrated circuits (3DICs) face challenges with excessive voltage drop in power distribution networks due to equivalent series resistance (ESR) and equivalent series inductance (ESL) in conductors, which current bypass capacitor placements, often remote from the internal power distribution network, fail to adequately address.
Innovation Solution
A capacitor interposer layer (CIL) is formed in a die-to-wafer 3DIC with trench capacitors and copper-to-copper bonds, reducing ESR and ESL by placing capacitors close to the power distribution network, thereby minimizing voltage droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bypass capacitors are placed underneath the substrate, then the device structure is simplified, but the equivalent series resistance and inductance increase causing excessive voltage drop
Solution Approach 1:
The patent transitions from planar capacitor placement (underneath substrate) to three-dimensional placement by positioning capacitors in an interposer layer between the substrate and the IC chip. This vertical dimensionality change reduces the electrical path length, thereby decreasing ESR and ESL while maintaining structural organization.
Solution Approach 2:
The interposer layer acts as an intermediary component between the substrate and the IC chip, housing the bypass capacitors in close proximity to the power distribution network. This intermediary structure enables optimal capacitor placement without requiring direct modification of the substrate or chip, resolving the voltage drop issue while preserving overall device architecture.
2Reliability
If capacitors are placed close to the power distribution network, then equivalent series resistance and inductance are reduced, but the device profile increases
Solution Approach 1:
The patent utilizes the vertical dimension by placing capacitors in an interposer layer between the substrate and chip, rather than extending the device profile horizontally. This three-dimensional arrangement achieves low ESR/ESL through close proximity while maintaining a compact overall device footprint.
Solution Approach 2:
The capacitor structures are nested within the interposer layer, which itself is positioned between the substrate and the IC chip. This nested arrangement integrates the capacitors into the existing device stack without significantly increasing the overall device profile, achieving close coupling to the power distribution network.
3Reliability
If copper-to-copper bonding is used for electrical connections, then connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent specifies copper-to-copper bonding with controlled parameters including bonding temperature, pressure, and time to optimize both connection reliability and manufacturability. By carefully controlling these parameters, the process achieves high reliability while remaining compatible with existing manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CIL placement effectively reduces voltage drops across the power distribution network, allowing for a low-profile device with improved capacitive density and reduced equivalent series resistance and inductance.
Implementation Method 1
Electrical connections between the wafer and the chip are formed using a copper-to-copper bond
Implementation Method 2
The CIL includes a trench capacitor comprising a plurality of trenches
Data Source
AI summary
A capacitor interposer layer (CIL) in a die-to-wafer three dimensional integrated circuit (3DIC) and methods of forming the same are disclosed. A CIL is formed in a wafer under a powder distribution network (PDN) die area of a chip. Electrical connections between the wafer and the chip are formed using a copper-to-copper bond. This placement allows the capacitor to be close to the PDN die area within the chip to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL), while permitting a relatively low profile device with reduced PDN voltage droop.