Capacitor Interposer Substrate Layout for Low-Noise IC Packaging
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Solution Overview
Problem
Integrated circuits (ICs) face noise issues in power distribution networks (PDN) due to current-resistance (IR) drop and parasitic inductance, leading to voltage droop and electromagnetic radiation interference, which can cause malfunctions and crosstalk.
Innovation Solution
The use of a capacitor interposer substrate with aligned external interconnects is introduced, which is placed between the die and the package substrate to minimize parasitic inductance and reduce IR drop by embedding capacitors closer to the die, thereby reducing PDN noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitors are mounted on or embedded within a package substrate, then decoupling capacitance is provided to reduce PDN noise, but parasitic inductance in the electrical path connection increases IR drop and PDN noise
Solution Approach 1:
A capacitor interposer substrate is introduced as an intermediary component between the die and the package substrate. This interposer substrate carries embedded decoupling capacitors and aligned external interconnects that electrically connect the die to the package substrate, thereby providing decoupling capacitance while minimizing parasitic inductance through optimized current paths.
Solution Approach 2:
The solution transitions from a two-dimensional layout on the package substrate to a three-dimensional stacked architecture using an interposer substrate. The interposer substrate is positioned between the die and package substrate, creating vertical interconnect paths that reduce the loop area and parasitic inductance compared to planar connections on the substrate surface.
2Reliability
If capacitor interposer substrate is disposed between die and package substrate to minimize distance and reduce parasitic inductance, then IR drop and PDN noise are reduced, but interconnect alignment and fabrication precision requirements increase
Solution Approach 1:
The capacitor interposer substrate serves multiple functions simultaneously: it provides mechanical support for the die, embeds decoupling capacitors for PDN noise reduction, and incorporates aligned external interconnects for electrical connection. This multi-functionality consolidates several components into one, reducing overall assembly complexity despite the precision required for the interposer itself.
3Area of stationary object
If aligned external interconnects are used on capacitor interposer substrate, then interconnect compatibility is maintained and footprint is minimized, but fabrication process complexity increases
Solution Approach 1:
The external interconnects on the capacitor interposer substrate are designed with specific geometric parameters including alignment, pitch, and layout locations that match the die and package substrate. This parameter matching enables direct compatibility between components without requiring design modifications, maintaining interconnect compatibility while minimizing the overall package footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces IR drop and PDN noise, maintaining interconnect compatibility and minimizing the footprint of the IC package while enhancing signal routing efficiency.
Implementation Method 1
embedded capacitor(s) that can provide a decoupling capacitance for a power distribution network (PDN) in the IC package
Implementation Method 2
This can reduce parasitic inductance in power signals between the embedded capacitor(s) and the die(s), which can reduce the IR drop in the PDN
Implementation Method 3
reduce current-resistance (IR) drop and voltage droop
Data Source
AI summary
Aspects disclosed herein include integrated circuit (IC) packages employing a capacitor interposer substrate with aligned external interconnects, and related fabrication methods. The IC package includes one or more semiconductor dies (“dies”) electrically coupled to a package substrate that supports electrical signal routing to and from the die(s). The capacitor interposer substrate is disposed between the die(s) and the package substrate. The die(s) is coupled to embedded capacitor(s) in the capacitor interposer substrate through die interconnects coupled to external interconnects of the capacitor interposer substrate. In exemplary aspects, the external interconnects on the outer surfaces of the capacitor interposer substrate are aligned. In this manner, the capacitor interposer substrate can maintain interconnect compatibility to the die(s) and package substrate if the die(s) and package substrate have a pattern of die interconnects and external interconnects that are designed to align with each other when coupled to each other.