Hybrid-Bonded Capacitor Interposer for Low-Parasitic Chip Connection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for connecting ultra-high-performance capacitors to chips result in parasitic inductances and resistances that degrade their performance, limiting efficiency.
Innovation Solution
An interposer with high-density capacitors integrated through hybrid bonding, featuring conductive vias, anodized metal layers, and a dense interconnection network for molecular bonding, reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wire bonding or metal ball connections are used to connect capacitors to chips, then the capacitors can be connected to the chip, but parasitic inductances (5-100 pH) and resistances (20-100 mOhms) are generated that degrade the capacitor performance
Solution Approach 1:
The patent merges the capacitor structure directly with the interposer substrate by integrating capacitor electrodes into the interposer's conductive layers. This integration eliminates the need for separate capacitor components and their connecting wires, thereby removing the parasitic inductances and resistances that would otherwise be introduced by wire bonding or metal ball connections.
Solution Approach 2:
The interposer serves as an intermediary structure that provides built-in capacitor elements through its conductive layers and dielectric materials. This intermediary structure allows direct electrical connection between the chip and the capacitor functionality embedded in the interposer, avoiding the need for external capacitor components and their problematic connections.
2Reliability
If high-density capacitors are integrated into the interposer through hybrid bonding, then parasitic inductances and resistances are minimized, but the manufacturing complexity increases
Solution Approach 1:
The interposer is designed to serve multiple functions simultaneously: it provides mechanical support for chip mounting, establishes electrical connections through conductive vias and tracks, and integrates capacitor functionality through its dielectric layers and conductive electrodes. This multi-functionality reduces the need for separate capacitor components and simplifies the overall system architecture despite the enhanced internal structure.
Solution Approach 2:
The patent utilizes changes in material parameters and structural parameters of the interposer to achieve capacitor functionality. By adjusting the dielectric constant of insulating layers, the thickness of conductive layers, and the geometry of conductive vias, the capacitor characteristics (capacitance value, ESL, ESR) are optimized without requiring additional discrete components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the efficiency of capacitors by minimizing parasitic inductances and resistances, allowing for high-density capacitive elements that optimize power transfer without degrading intrinsic performance.
Implementation Method 1
each insulating region of the first layer is made of an anodized metal
Implementation Method 2
contact pads adapted to molecular bonding
Data Source
AI summary
An interposer including capacitors having a density greater than 700 nF/mm{circumflex over ( )}2. advantageously greater than 1 μF/mm{circumflex over ( )}2. the interposer being adapted to being bonded to a chip by hybrid bonding.