Hybrid-Bonded Capacitor Interposer for Low-Parasitic Chip Power Delivery
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Solution Overview
Problem
Conventional methods for connecting high-performance capacitors to electronic devices result in significant parasitic inductances and resistances, degrading their performance due to the use of wire connections or metal balls, which exceed the parasitic values of high-performance capacitors.
Innovation Solution
An interposer with integrated high-density capacitors, fabricated using a substrate with conductive vias and anodized metal layers, connected via a dense network of conductive tracks and pads for molecular bonding, minimizing parasitic inductances and resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire connections or metal balls are used to connect capacitors to chips, then the connection is simple and reliable, but parasitic inductances (5 to 100 pF) and resistances (20-100 mΩ) are generated that degrade capacitor performance
Solution Approach 1:
The patent merges the capacitor structure directly with the interposer substrate, eliminating separate wire connections and metal balls. The capacitor electrodes are formed as integrated conductive regions within the interposer layers, creating a unified structure that removes the harmful parasitic elements while maintaining reliable electrical connection.
Solution Approach 2:
The patent introduces an intermediate conductive layer system within the interposer that serves as a mediator between the capacitor electrodes and the chip connection points. This intermediate network of conductive tracks and vias provides low-parasitic pathways that replace the traditional high-parasitic wire and ball grid connections.
2Reliability
If high-density capacitors are integrated into the interposer, then power delivery is optimized and parasitic values are reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent changes the physical and electrical parameters of the interposer structure by integrating capacitor electrodes directly into the interposer layers. This involves modifying the conductive layer configuration, adding capacitive structures between existing layers, and reconfiguring the interconnection network to achieve high capacitor density while maintaining manufacturability through standard semiconductor fabrication processes.
3Ease of manufacture
If traditional wire connections are used, then the connection method is simple and easy to manufacture, but the parasitic inductances and resistances exceed the parasitic values of high-performance capacitors
Solution Approach 1:
The patent replaces the mechanical wire connection system with an integrated planar conductive structure. Instead of using physical wires and solder balls that require mechanical assembly, the capacitor electrodes and interconnection network are formed as thin-film conductive layers patterned during semiconductor fabrication, eliminating the mechanical connection step while achieving lower parasitic values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the connection of high-performance capacitors with reduced parasitic inductances and resistances, optimizing power supply efficiency and maintaining intrinsic performance without increasing the interposer size.
Implementation Method 1
each insulating region of the first layer is made of an anodized metal
Implementation Method 2
the interposer being adapted to be fixed to a chip by hybrid bonding
Data Source
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AI summary
The present description relates to an interposer (12) comprising capacitors (32) having a density greater than 700 nF/mm^2, advantageously greater than 1 µF/mm^2, the interposer being adapted to be fixed to a chip (14) by hybrid bonding.