Capacitor With Intersecting Trenches On Both Surfaces

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Solution Overview

Problem

Existing capacitor designs face challenges in achieving a balance between high electric capacity and mechanical strength, particularly in the configuration of recesses and through holes on a silicon substrate, which affects the formation of conductive and dielectric layers and the overall performance of the capacitor.

Innovation Solution

The capacitor design incorporates a substrate with intersecting recesses forming through holes, where the first and second recesses on the substrate's surfaces are connected, and additional through holes on the side walls, allowing for a stacked structure of conductive and dielectric layers that enhance electric capacity while maintaining mechanical integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If recesses and through holes are formed on the silicon substrate to increase capacitance, then electric capacity is improved, but mechanical strength deteriorates

Engineering Contradiction:
Improveelectric capacityVSAvoidmechanical strength
Core Design Contradiction:
Quantity of substanceVSStrength

Solution Approach 1:

The patent forms recesses not only on the front surface but also on the back surface of the silicon substrate, utilizing the third dimension (depth from both surfaces) to increase capacitance. Through holes connect these recesses, creating a three-dimensional capacitor structure that maximizes surface area for charge storage while distributing mechanical stress throughout the substrate thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The silicon substrate is segmented into multiple regions with recesses formed at different locations (front surface, back surface, and side walls). This segmentation allows the capacitor structure to be distributed throughout the substrate volume, increasing total capacitance while maintaining structural integrity through the remaining substrate material.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If complex trench structures are formed on both surfaces, then capacitance density is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecapacitance densityVSAvoidmanufacturing steps
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines the formation of front surface recesses, back surface recesses, and side wall structures into a unified manufacturing process. By using a single mask pattern and etching step that penetrates through the substrate, multiple capacitor regions are formed simultaneously, reducing the total number of manufacturing steps while achieving high capacitance density.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The through holes formed in the substrate serve multiple functions: they connect the front and back surface recesses to form complete capacitor structures, provide pathways for conductive layers, and enable electrical connection between opposing electrodes. This multi-functionality reduces the need for separate structural elements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11508525B2Capacitor having trenches on both surfaces
Publication Date: 2022.11.22 KK TOSHIBA
  • US11508525B2 patent drawing
  • US11508525B2 patent drawing
  • US11508525B2 patent drawing

AI summary

A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.