Capacitor Laminated Structure on Wall Support for High Density
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Solution Overview
Problem
Existing capacitor manufacturing techniques struggle to meet the demands of high-end applications requiring increased capacitance density in modern electronic systems with multi-functions, high integration, low power consumption, and microminiaturization.
Innovation Solution
A capacitor design featuring a laminated structure with alternately stacked conductive and dielectric layers on a wall-shaped support, allowing for high capacitance in a small device size, and simplifying the capacitor structure by using the support as an electrode plate, with an interconnection structure connecting the electrodes through dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor structures are used, then manufacturing processes are simple, but capacitance density is low and cannot meet high-end application requirements
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertically stacked configurations. Multiple dielectric layers and conductive layers are stacked vertically to form a laminated structure, effectively utilizing the third dimension (height) to increase capacitance density without proportionally increasing footprint area. This dimensional transition allows achieving higher capacitance values in compact packages.
Solution Approach 2:
The patent employs nested structures where conductive layers are embedded within dielectric layers in an alternating stacked configuration. The support structure serves as a central element around which multiple capacitor units are nested in vertical layers. This nesting approach maximizes the use of available space and achieves high capacitance density through compact hierarchical arrangement.
2Volume of moving object
If capacitor size is reduced for microminiaturization, then integration is improved, but maintaining high capacitance becomes difficult
Solution Approach 1:
The patent compensates for reduced footprint area by extending capacitor structures vertically in the third dimension. Multiple stacked layers increase the effective capacitance volume without proportionally increasing the horizontal footprint, enabling micro-miniaturization while maintaining or enhancing capacitance values through vertical scaling.
Solution Approach 2:
The patent employs composite laminated structures combining multiple dielectric materials with different properties in alternating layers. This composite approach optimizes the balance between capacitance density, physical size, and electrical performance characteristics, allowing compact designs to achieve high capacitance through material optimization rather than simply increasing volume.
3Quantity of substance
If more dielectric and conductive layers are added to increase capacitance, then capacitance density improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the capacitor structure into modular repeating units of dielectric-conductive layer pairs stacked vertically. This segmentation into standardized building blocks simplifies manufacturing by enabling repetitive deposition processes and facilitating modular assembly. Each layer pair can be fabricated using similar process steps, reducing overall manufacturing complexity despite the increased number of layers.
Solution Approach 2:
The patent incorporates a support structure formed in advance that serves as a template or scaffold for subsequent layer deposition. This preliminary action establishes the vertical architecture before adding multiple dielectric and conductive layers, providing structural guidance that simplifies the subsequent lamination process and ensures proper alignment of multiple interfaces.
Data Source
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AI summary
Embodiments of the present application provide a capacitor and a producing method therefore. The capacitor includes: a first electrode and a second electrode respectively configured to connect an external circuit; at least one support, the at least one support being a pillar-shaped structure or a wall-shaped structure; a laminated structure including at least one dielectric layer and at least one conductive layer; and an interconnection structure configured to electrically connect the first electrode to the at least one support or a first conductive layer of the at least one conductive layer, and to electrically connect the second electrode to a second conductive layer of the at least one conductive layer, where the second conductive layer is connected to the at least one support or the first conductive layer electrically connected to the first electrode through a dielectric layer of the at least one dielectric layer. According to a capacitor of an embodiment of the present application, the capacitor is formed using a laminated structure, which could obtain a great capacitance value in a case of a small device size, thereby improving capacitance density of the capacitor. In addition, the at least one support serves as one electrode plate of the capacitor, which simplifies a structure of the capacitor.