Capacitor Landing Pad Stacking for DRAM Area Utilization
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Solution Overview
Problem
Existing methods for forming capacitors in semiconductor memory devices face challenges in reducing electrical shorts and effectively utilizing the semiconductor substrate area, especially under submicron design rules, which can lead to deteriorated electrical characteristics due to conductive layer patterns.
Innovation Solution
The solution involves stacking landing pads, buried plugs, and lower electrodes in a specific configuration on the semiconductor substrate, where the landing pads have larger upper surfaces than central landing pads, and the buried plugs are offset, allowing the lower electrodes to overlap the landing pads and reducing electrical shorts while maintaining capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductive layer patterns are placed below lower electrodes to effectively use upper spaces on semiconductor substrate, then substrate area utilization is improved, but electrical shorts of conductive layer patterns occur deteriorating electrical characteristics
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration. Landing pads are formed at different vertical levels (first landing pad at lower level, second landing pad at higher level), allowing conductive structures to extend in the vertical dimension. This dimensional change enables effective substrate area utilization while maintaining electrical isolation between conductive elements through the interlayer insulating layer, thereby preventing electrical shorts.
Solution Approach 2:
An interlayer insulating layer is introduced as an intermediary between the first and second landing pads. This insulating layer acts as a mediator that provides electrical isolation between the conductive landing pads while allowing them to be positioned in close proximity for effective area utilization. The insulating layer enables the system to achieve both high density and reliable electrical isolation.
2Productivity
If design rule is scaled down to below submicron dimensions to increase device density, then device integration is improved, but electrical shorts of lower electrodes occur due to reduced process margins
Solution Approach 1:
The patent employs three-dimensional stacking with landing pads positioned at different vertical levels connected by conductive plugs. This vertical arrangement increases device integration density without requiring proportional reduction in lateral dimensions, thereby maintaining adequate process margins. The vertical separation provided by interlayer insulating layers ensures reliable electrical isolation even at submicron dimensions.
Solution Approach 2:
The interlayer insulating layer is formed in advance between the first and second landing pads before final electrode formation. This preliminary insulation structure is established to prevent potential electrical shorts before they can occur during subsequent processing steps, ensuring reliability is built into the structure from the outset rather than relying on tight tolerances alone.
3Quantity of substance
If lower electrode surface area is maintained the same size to maintain capacitance as design rule decreases, then capacitance is preserved, but electrical shorts occur more frequently
Solution Approach 1:
The patent maintains capacitance by extending the lower electrode structure vertically through conductive plugs that connect landing pads at different levels, rather than increasing lateral surface area. This vertical extension allows the electrode to achieve sufficient capacitance while the lateral dimensions remain small enough to prevent electrical shorts, effectively decoupling the capacitance requirement from the area constraint.
Data Source
AI summary
A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.