Capacitor-Less DRAM Charge-Trapping Structure for Memory Retention
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Solution Overview
Problem
As integrated circuit devices are downscaled, the complexity of capacitor formation in dynamic random-access memory (DRAM) devices increases, leading to leakage current issues, prompting the need for capacitor-less DRAM devices with improved retention characteristics.
Innovation Solution
The integration of a capacitor-less DRAM device with a single transistor, featuring a trapping layer with an oxide semiconductor, a gate insulation layer, and a bit line, where the channel layer has a specific bandgap energy and the trapping layer has a greater bandgap energy, enabling charge trapping and storage with excellent retention characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor height is increased to improve retention characteristics, then memory retention is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The invention extracts and eliminates the capacitor component from the DRAM structure, transitioning from a capacitor-based memory cell to a transistor-only structure. This removes the manufacturing complexity associated with forming tall capacitors while maintaining retention characteristics through the trapping layer mechanism.
Solution Approach 2:
The invention changes the fundamental operating parameter from capacitor charge storage to trapping layer charge trapping. By utilizing the bandgap energy difference between the channel layer and trapping layer, the system achieves charge retention without requiring tall capacitors, thus improving retention while simplifying manufacturing.
2Reliability
If capacitor height is increased to reduce leakage current, then leakage current is reduced, but manufacturing difficulty increases
Solution Approach 1:
The invention removes the capacitor from the structure entirely, replacing it with a trapping layer that achieves leakage current control through bandgap energy differences rather than physical capacitor height, thereby eliminating the associated manufacturing difficulties.
Solution Approach 2:
The invention employs composite material structures with different bandgap energies (channel layer with first bandgap energy, trapping layer with second bandgap energy greater than the first) to achieve leakage control without requiring tall capacitors, simplifying the formation process.
3Productivity
If device downsizing is implemented to increase integration density, then integration density is improved, but retention characteristics deteriorate
Solution Approach 1:
The invention changes the charge storage mechanism from capacitor-based to trapping layer-based, utilizing bandgap energy differences to maintain retention characteristics even as device dimensions are reduced for higher integration density.
Solution Approach 2:
The invention uses composite material structures with specific bandgap energy relationships to maintain effective charge trapping and retention characteristics in downscaled devices, enabling high integration density without sacrificing reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory retention and integration density by effectively trapping charges using a deep trap level in the trapping layer, resulting in improved memory window and retention characteristics for capacitor-less DRAM devices.
Implementation Method 1
the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy
Implementation Method 2
effectively trapping charges using a deep trap level in the trapping layer
Data Source
AI summary
Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.