Capacitor-less DRAM with Segmented Gate for Noise Reduction
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Solution Overview
Problem
In capacitor-less, 1-transistor DRAM memory devices, capacitive coupling between the word line and the floating body leads to noise transmission during read/write operations, causing erroneous data reading and writing, making it difficult to implement these devices practically.
Innovation Solution
The memory device employs a semiconductor structure with a vertical or horizontal semiconductor base, impurity layers, gate insulating layers, and gate conductor layers to control voltages for page write and erase operations, utilizing a forced inversion type sense amplifier with charge sharing to enhance read determination and reduce capacitive coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor-less 1-transistor DRAM memory cells are used to achieve higher integration, then device density is improved, but capacitive coupling noise between word line and floating body causes erroneous data reading and writing
Solution Approach 1:
The gate structure is divided into two separate gate electrodes (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows independent voltage application to each gate, enabling precise control of the channel formation and reducing unwanted capacitive coupling effects on the floating body while maintaining high device density through the vertical channel structure.
Solution Approach 2:
The invention changes the voltage parameters applied to the two gates differently during read and write operations. By applying specific voltage combinations to the first and second gates, the channel is selectively formed or pinched off, and the capacitive coupling noise is minimized through optimized voltage timing and magnitude, thereby improving data accuracy while maintaining high integration.
2Quantity of substance
If vertical channel SGT transistors are used to achieve higher integration, then device density is improved, but capacitive coupling between word line and floating body increases causing noise
Solution Approach 1:
The vertical channel transistor gate is segmented into two independent gate electrodes positioned at different locations along the vertical channel. This segmentation allows the word line to be split into two separately controllable gates, reducing the effective capacitive coupling area between the word line and floating body while maintaining the vertical channel structure for high density.
Solution Approach 2:
The two-gate structure acts as an intermediary control mechanism between the word line and the floating body. By controlling the channel formation through two separate gates rather than a single gate, the invention mediates the capacitive coupling effect, allowing selective channel formation that reduces noise while maintaining the benefits of vertical channel transistors for high integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces capacitive coupling noise, allowing for accurate and reliable data storage by maintaining a sufficient potential difference margin between data states, thus enabling practical implementation of capacitor-less DRAM memory cells.
Implementation Method 1
capacitive coupling between the word line and the floating body leads to noise transmission during read/write operations
Implementation Method 2
a first impurity layer and a second impurity layer located on opposite ends of the semiconductor base
Data Source
AI summary
A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.