Capacitor-less DRAM Trench Structure Offset Spacer Alignment
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Solution Overview
Problem
The integration of DRAM devices is hindered by the short channel effect and complexity of capacitor formation processes, limiting further increases in integration degree and reliability due to leakage currents.
Innovation Solution
A capacitor-less DRAM device is designed with a trench structure and offset spacers, where the source and drain regions are formed on both sides of the offset spacer without overlapping the gate electrode, allowing for a self-aligned channel region and reduced leakage currents, enabling high integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of the transistor is reduced to increase integration degree, then the integration degree increases, but the short channel effect occurs causing leakage current and reliability degradation
Solution Approach 1:
The invention transitions from planar transistor structures to vertically stacked FinFET structures, utilizing the third dimension (height) to increase effective channel width while maintaining small footprint. The FinFET configuration with vertical fins allows better gate control over the channel, reducing short channel effects and leakage current while achieving higher integration density.
Solution Approach 2:
The invention implements nested capacitor structures where dielectric layers are stacked vertically between source and drain regions, creating multiple storage nodes within a small area. The capacitor structure is embedded within the transistor architecture, with insulating layers nested between conductive regions, maximizing storage capacity without increasing planar footprint.
2Productivity
If complex capacitor formation techniques are used to increase integration degree, then the effective capacity increases, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention merges the capacitor formation process with the transistor manufacturing process. The same dielectric layers used for gate insulation are also used for capacitor formation, and the same etching and deposition processes serve both transistor and capacitor structures. This integration eliminates separate capacitor formation steps, reducing device complexity while maintaining high integration density.
Solution Approach 2:
The dielectric layers serve multiple functions: they provide gate insulation for the FinFET transistor, form capacitor dielectric for data storage, and provide electrical isolation between different structures. The offset spacers serve both as alignment references for channel formation and as structural elements defining the capacitor geometry, reducing the number of dedicated components needed.
3Productivity
If the transistor size is reduced, then the integration degree increases, but the manufacturing precision requirements increase due to short channel effects
Solution Approach 1:
The invention uses preliminary patterning steps to define the fin structure geometry before final transistor fabrication. Offset spacers are formed in advance to pre-establish the channel width and alignment references, ensuring consistent dimensions even at reduced sizes. The sequential formation of dielectric layers with controlled thicknesses provides built-in dimensional control for subsequent processing steps.
Solution Approach 2:
The invention changes the critical dimension control from planar width to vertical fin height and thickness parameters. By controlling the fin thickness and height rather than lateral dimensions, the design achieves better scalability to smaller sizes. The vertical dimension allows more relaxed lithographic requirements while maintaining precise dimensional control through epitaxial growth and atomic layer deposition techniques.
Data Source
AI summary
Provided is a capacitor-less DRAM device including: an insulating layer formed on a semiconductor substrate; a silicon layer formed on the insulating layer, wherein a trench is formed inside the silicon layer; and an offset spacer formed on both sidewalls of the trench and protruded upward through the silicon layer. A gate insulating layer is formed on a bottom of the trench, and a gate electrode is formed to be buried in the gate insulating layer and in the trench and the offset spacer. A source region and a drain region are formed in the silicon layer on both sides of the offset spacer so as not to overlap with the gate electrode. A channel region is formed in the silicon layer below the gate insulating layer to be self-aligned with the gate electrode.