Capacitor-Less Memory Cell Using Floating Body Charge Storage
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Solution Overview
Problem
The miniaturization of DRAM chips poses challenges in maintaining required storage capacitance without increasing the dimensions of capacitors, leading to expensive and defect-prone fabrication processes, and existing technologies struggle to integrate high-density memory cells with logic devices using compatible fabrication techniques.
Innovation Solution
The development of capacitor-less memory cells using a partial silicon-on-insulator (SOI) technique, where a pass transistor and a read/write enable transistor are formed on a physically isolated active area, storing logic states as charge in a floating body area, eliminating the need for capacitors and allowing for integration with logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If capacitor dimensions are reduced to increase miniaturization, then area occupation is reduced, but storage capacitance becomes insufficient
Solution Approach 1:
The patent transitions from planar capacitor design to three-dimensional vertical capacitor structure. The capacitor extends deeply into the substrate with depth significantly greater than width, utilizing the vertical dimension to increase storage capacitance while maintaining small footprint area occupation.
Solution Approach 2:
The capacitor is nested within the memory cell structure, with the capacitor body embedded in the substrate and the transistor positioned above it. This nested arrangement allows both components to occupy overlapping spatial regions, maximizing area utilization.
2Quantity of substance
If capacitor depth is increased to maintain capacitance levels, then storage capacitance is maintained, but manufacturing complexity and defect risk increase
Solution Approach 1:
The capacitor formation process is segmented into distinct stages: forming the capacitor body in the substrate, creating the insulating layer, depositing the electrode material, and forming the top electrode. This segmentation allows each step to be optimized independently and integrated with standard CMOS fabrication processes.
Solution Approach 2:
The fabrication process is designed to be universal with standard CMOS technology. The same deposition, etching, and doping techniques used for transistor fabrication are also used for capacitor formation, eliminating the need for specialized processes and enabling co-fabrication of memory and logic devices.
3Quantity of substance
If specialized capacitor fabrication processes are used, then capacitance requirements are met, but integration with logic devices becomes difficult
Solution Approach 1:
The capacitor fabrication process uses the same material systems and processing techniques as standard CMOS logic fabrication. Polysilicon electrodes, silicon dioxide insulators, and standard doping processes are employed, making the capacitor structures fully compatible with logic device fabrication on the same substrate.
Solution Approach 2:
The memory cell and logic device fabrication processes are merged into a single integrated flow. The capacitor and transistor are formed simultaneously using shared process steps, and the same fabrication equipment and material deposition techniques are used for both memory and logic portions of the chip.
Data Source
AI summary
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.