Capacitor-Less Memory Cell Layout for Voltage-Sensed Random Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving improved performance and integration, particularly in capacitor-less designs that require complex current sense amplifiers and struggle with random access and space efficiency.
Innovation Solution
A semiconductor memory device is designed with a first and second metal-oxide semiconductor film, intersecting gate electrodes, and a charge storage film within the gate dielectric, allowing for improved performance and integration by enabling random access and using a voltage sense amplifier for efficient data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a capacitor-less semiconductor memory device is designed, then the device complexity is reduced by eliminating the capacitor, but the measurement precision deteriorates due to the need for complex current sense amplifiers
Solution Approach 1:
The patent transitions from a planar memory cell design to a three-dimensional stacked configuration with vertical channel structures and multiple gate electrodes positioned at different heights. This vertical stacking enables random access capability while maintaining capacitor-less operation, resolving the contradiction between simplified device structure and precise data reading
2Area of stationary object
If a voltage sense amplifier is used instead of a current sense amplifier, then the space efficiency improves, but the measurement precision deteriorates
Solution Approach 1:
The patent changes the sensing parameter from current measurement to voltage measurement by utilizing the threshold voltage shift in the metal-oxide semiconductor channel caused by charge trapping. This parameter change enables the use of compact voltage sense amplifiers while maintaining adequate measurement precision through the high sensitivity of metal-oxide semiconductor threshold voltage to trapped charge
3Adaptability or versatility
If random access capability is enabled in the memory device, then the adaptability improves, but the device complexity increases due to additional gate electrodes and wiring structures
Solution Approach 1:
The patent segments the gate control into multiple independent gate electrodes positioned at different vertical levels, each capable of independently selecting specific memory regions. This segmentation enables random access to different memory blocks without requiring a single complex gate structure, as each gate electrode can be controlled separately to access specific areas
4Reliability
If metal-oxide semiconductor materials are used in the channel layer, then the leakage current characteristics improve, but the manufacturing precision deteriorates due to material deposition challenges
Solution Approach 1:
The patent employs composite material structures including metal-oxide semiconductor channels combined with high-k gate dielectric materials and various interface layers. These composite structures mitigate the manufacturing challenges of metal-oxide semiconductors by providing buffer layers and optimized interfaces that reduce deposition sensitivity while maintaining the superior leakage current characteristics of metal-oxide channel materials
Data Source
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AI summary
A capacitor-less semiconductor memory device and a method for fabricating the same are provided. The semiconductor memory device includes a first metal-oxide semiconductor film (142), a second metal-oxide semiconductor film (144) spaced apart from the first metal-oxide semiconductor film (142), a first gate electrode (182) intersecting the first metal-oxide semiconductor film (142) and the second metal-oxide semiconductor film (144), a first gate dielectric film (132) interposed between the first metal-oxide semiconductor film (142) and the first gate electrode (182), a charge storage film (150) in the first gate dielectric film, the charge storage film (150) extending along at least a portion of the first metal-oxide semiconductor film (142) and connected to the second metal-oxide semiconductor film (144), a second gate electrode (184) spaced apart from the first gate electrode (182) and intersecting the second metal-oxide semiconductor film (144), and a second gate dielectric film (134) interposed between the second metal-oxide semiconductor film (144) and the second gate electrode (184).