Capacitor Line Orientation Reducing Parasitic Capacitance in Display Apparatus
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Solution Overview
Problem
In liquid crystal display apparatuses, the configuration where gate bus lines extend along the longitudinal direction of pixel electrodes and source bus lines extend along the transverse direction increases the number of crossings, leading to increased parasitic capacitance and signal delay, particularly when CS bus lines cross source bus lines, causing a greater load on the source bus line.
Innovation Solution
The display apparatus includes a pixel electrode with a longitudinal shape, a switching element connected to it, a scanning line extending along the longitudinal direction, an image line extending along the transverse direction, a liquid crystal layer with multiple domains of aligned liquid crystal molecules, an alignment boundary portion, an alignment film, and a capacitor line that extends along the transverse direction and overlaps with the pixel electrode and the alignment boundary portion, reducing parasitic capacitance by not crossing the source line but crossing the gate line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the gate bus line extends along the longitudinal direction of the pixel electrode and the source bus line extends along the transverse direction, then the number of gate bus lines increases, but the number of source bus lines is reduced, however this configuration increases the number of crossings between source and gate bus lines, leading to increased parasitic capacitance and signal delay
Solution Approach 1:
The patent applies dimensionality change by routing the capacitor line in the transverse direction (perpendicular to the longitudinal gate lines) instead of parallel to them. This spatial reconfiguration in a different dimensional orientation allows the capacitor line to overlap with gate lines rather than cross source lines, thereby reducing parasitic capacitance effects on the source bus while maintaining the reduced source line count.
Solution Approach 2:
The capacitor line serves as an intermediary element that mediates the relationship between the pixel electrode and the gate bus lines. By positioning the capacitor line to overlap with gate lines rather than cross source lines, it acts as a buffer that reduces the harmful parasitic capacitance interaction between source and gate bus lines, thus mitigating signal delay without requiring additional source lines.
2Ease of manufacture
If the capacitor line extends in parallel to the gate bus line, then the capacitor line crosses the source bus line, but this configuration causes greater load on the source bus line due to parasitic capacitance generated between the source bus line and the gate bus line
Solution Approach 1:
The patent changes the dimensional relationship between the capacitor line and source line from a crossing configuration to a parallel configuration. By extending the capacitor line in the transverse direction (parallel to source lines rather than crossing them), it eliminates the harmful parasitic capacitance interaction that occurs when capacitor lines cross source lines, while still achieving the necessary capacitive coupling through overlap with gate lines.
Solution Approach 2:
The patent converts the potential harm of having capacitor lines cross source lines into a benefit by reconfiguring the capacitor line to overlap with gate lines instead. This transformation eliminates the parasitic capacitance problem while maintaining the essential function of the capacitor line, effectively turning a harmful configuration into a beneficial one by changing the spatial relationship.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal delay in the source line by avoiding parasitic capacitance between the source and capacitor lines, while also improving display quality by minimizing display unevenness and luminance reduction caused by alignment boundary portions.
Implementation Method 1
a liquid crystal layer that includes liquid crystal molecules; a plurality of domains that are different in alignment direction of the liquid crystal molecules
Implementation Method 2
reduces signal delay in the source line by avoiding parasitic capacitance between the source and capacitor lines
Data Source
AI summary
A display apparatus includes: a pixel electrode; a switching element that is connected to the pixel electrode; a scanning line that transfers a signal by which the switching element is driven; an image line that transfers a signal by which the pixel electrode is charged; a liquid crystal layer that includes liquid crystal molecules; a plurality of domains that are different in alignment direction of the liquid crystal molecules when a voltage is applied to the liquid crystal layer; an alignment boundary portion that is positioned in a boundary of the plurality of domains; an alignment film that aligns the liquid crystal molecules, and a capacitor line that extends along the transverse direction and is arranged so as to be overlapped with the pixel electrode with an insulating film in between and overlapped with at least a part of the alignment boundary portion.