Capacitor-Based Dynamic Memory with Dual-Threshold Write and Read Gates
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Solution Overview
Problem
Conventional dynamic random access memories (DRAMs) face challenges in maintaining sufficient storage capacity and stability due to quantum tunneling effects and manufacturing complexity as capacitors shrink, and existing 1S1C memories have short data hold times due to large leakage currents from ovonic threshold switch selectors.
Innovation Solution
A dynamic memory structure with separate write and read gating devices, each having unidirectional threshold switch characteristics, where the write gating device's conduction threshold voltage is less than that of the read gating device, reducing sub-threshold leakage and prolonging data retention time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bidirectional gating device is used for both writing and reading, then the device structure is simplified, but the data hold time is reduced due to large leakage current
Solution Approach 1:
The patent divides the single gating device into two separate unidirectional gating devices: a write gating device for writing operations and a read gating device for reading operations. This segmentation allows each device to be optimized for its specific function, with the read gating device having a higher threshold voltage to minimize leakage current and extend data hold time, while the write gating device can be optimized for writing efficiency.
2Speed
If the conduction threshold voltage of the gating device is reduced to improve writing efficiency, then writing speed increases, but leakage current increases and data hold time decreases
Solution Approach 1:
The patent applies different conduction threshold voltages to different gating devices based on their specific functions. The write gating device has a lower conduction threshold voltage (first threshold voltage) to enable efficient writing operations, while the read gating device has a higher conduction threshold voltage (second threshold voltage) to minimize leakage current during data storage. This local differentiation of electrical properties resolves the contradiction between writing speed and data hold time.
3Quantity of substance
If capacitor size is reduced to increase memory density, then integration level improves, but quantum tunneling effect increases causing data loss
Solution Approach 1:
The patent changes the electrical parameters of the gating devices, specifically setting different conduction threshold voltages for write and read operations. By optimizing these voltage parameters, the system can maintain stable data storage in smaller capacitors by preventing excessive leakage current that would otherwise accelerate quantum tunneling effects and lead to data loss, thus improving reliability without sacrificing density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases the types of gating devices available and significantly extends the data hold time in DRAMs by minimizing leakage currents, improving the performance and reducing the refresh frequency.
Implementation Method 1
the write gating device and the read gating device are both unidirectionally conducted, and conduction modes of the write gating device and the read gating device are both threshold-on; the threshold-on means that only when a potential of the second terminal of the write gating device is higher than a potential of the first terminal of the write gating device by a conduction threshold voltage of the write gating device, the write gating device is conducted
Implementation Method 2
the write gating device and the read gating device are both unidirectionally conducted
Data Source
AI summary
Provided is a dynamic memory structure and an operating method thereof. The dynamic memory structure includes a write gating device, a read gating device, and a capacitor. A first terminal of the write gating device, a first terminal of the read gating device, and a first terminal of the capacitor are connected together; a second terminal of the write gating device is a data writing end; a second terminal of the read gating device is a data reading end; and a second terminal of the capacitor is a gating end and connected to a word line. The write gating device and the read gating device are both unidirectionally conducted, and conduction modes of the write gating device and the read gating device are both threshold-on. A conduction threshold voltage of the write gating device is less than a conduction threshold voltage of the read gating device.