Capacitor Integrated with Memory Gate Structure
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Solution Overview
Problem
As semiconductor components shrink and integration increases, existing capacitor structures face challenges in achieving desired capacitance, operation power, process simplification, and reducing processing costs.
Innovation Solution
A capacitor is formed using a memory structure with a first control gate and a first selective gate as electrodes, and a first dielectric layer vertically sandwiched between them, integrating the capacitor process into a memory process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional capacitor structures (MIM, PIP, or MOS) are used in high-density integration, then process compatibility is improved, but achieving desired capacitance and operation power becomes difficult
Solution Approach 1:
The patent merges the capacitor structure with the memory cell structure by using the control gate and selective gate of the memory cell as the two electrodes of the capacitor, and the dielectric layer between them as the capacitor dielectric. This integration allows the capacitor to be formed within the memory cell footprint, achieving both high-density integration and desired capacitance values without requiring separate capacitor fabrication processes.
2Productivity
If component sizes shrink to increase integration, then device density is improved, but achieving desired capacitance and operation power becomes more difficult
Solution Approach 1:
The patent transitions from planar capacitor electrode arrangement to a vertical arrangement where the dielectric layer is positioned between the control gate and selective gate in the vertical dimension. This vertical stacking enables the capacitor to achieve sufficient capacitance within the reduced lateral footprint, maintaining performance while increasing integration density.
3Reliability
If separate capacitor fabrication processes are used, then capacitor quality can be optimized, but processing cost and complexity increase
Solution Approach 1:
The patent makes the memory cell structure serve dual functions: as the active memory element and as the capacitor structure. The control gate and selective gate of the memory cell simultaneously function as memory control elements and capacitor electrodes, eliminating the need for separate capacitor fabrication processes and reducing overall processing complexity while maintaining capacitor quality.
4Reliability
If separate capacitor fabrication processes are used, then capacitor performance can be optimized, but processing cost increases
Solution Approach 1:
The patent combines capacitor fabrication with memory cell fabrication into a single integrated process. By using the existing memory cell gates and dielectric layers to form the capacitor, the method eliminates separate capacitor fabrication steps, reduces processing cost, and maintains capacitor performance through the inherent quality of the memory structure materials and processes.
Data Source
AI summary
A device including a capacitor includes an isolation structure, a first control gate, a first selective gate and a first dielectric layer. The isolation structure is disposed in a substrate. The first control gate and the first selective gate are disposed directly above the isolation structure. The first dielectric layer is vertically sandwiched by the first control gate and the first selective gate, thereby constituting the capacitor. The present invention also provides a method of forming the device including the capacitor.