Capacitor-Based Memory Device for Low Power Consumption
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Solution Overview
Problem
Semiconductor devices face increased power consumption due to off-state currents as the size of central processing units and buffer memory devices grow, and existing methods for reducing power consumption, such as using nonvolatile memory, are complex or inefficient for short power outages.
Innovation Solution
A memory device with a capacitor that stores data and a switching element to control electric charge, allowing data to be saved and retrieved without the need for external memory, reducing power consumption by minimizing off-state current during power outages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of central processing unit or buffer memory device is increased, then processing capability is improved, but total off-state current increases and power consumption is increased
Solution Approach 1:
The patent applies preliminary action by transferring data from the volatile buffer memory device to the nonvolatile memory device before stopping the power supply. This ensures that data is preserved in advance, allowing the buffer memory to be powered down completely, thereby eliminating off-state current consumption while maintaining data availability for future operations
Solution Approach 2:
The patent changes the operational state parameter of the buffer memory device from continuous power supply to intermittent power supply. By switching between powered and unpowered states based on operational needs, the system reduces average power consumption while maintaining processing capability through rapid data retrieval from nonvolatile memory when needed
2Reliability
If nonvolatile memory device is used to save data before stopping power supply, then data retention is improved, but manufacturing process becomes complex
Solution Approach 1:
The patent merges the buffer memory device and nonvolatile memory device into a single integrated memory system. This combination allows the system to leverage the high-speed characteristics of volatile memory for active operations while utilizing the data retention capabilities of nonvolatile memory, all within a unified manufacturing process that avoids the complexity of separate systems
Solution Approach 2:
The integrated memory system performs multiple functions: it operates as a high-speed buffer memory when powered, and automatically preserves data in nonvolatile storage when powered down. This multi-functionality eliminates the need for separate volatile and nonvolatile memory systems, simplifying the overall manufacturing process while maintaining both speed and data retention capabilities
3Reliability
If data is transferred to external memory device, then data retention during long power outage is improved, but data transfer time increases and is not suitable for short power outages
Solution Approach 1:
The patent introduces a nonvolatile memory device as an intermediary between the volatile buffer memory and external memory systems. This intermediary provides rapid data transfer capabilities compared to external memory, enabling quick data preservation during short power outages and fast retrieval when power is restored, thereby eliminating the time loss associated with external memory transfers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables reliable data retention and reduced power consumption by eliminating the need for external memory and minimizing off-state current, even during short power outages, thus enhancing the efficiency of semiconductor devices.
Implementation Method 1
a capacitor which stores data of the memory element
Implementation Method 2
a switching element which controls supply of electric charge to the capacitor, holding of electric charge in the capacitor, and release of electric charge from the capacitor
Implementation Method 3
a memory element including a plurality of logic elements each of which generates an output potential by inverting a polarity of an input potential
Data Source
AI summary
A memory device with low power consumption is provided. A memory device includes a first logic element generating an output potential by inverting a polarity of a potential of a signal including data in accordance with a first clock signal; second and third logic elements holding the output potential generated by the first logic element; a switching element including a transistor; and a capacitor storing the data by being supplied with the output potential of the first logic element which is held by the second and third logic elements via the switching element. The second logic element generates an output potential by inverting a polarity of an output potential of the third logic element in accordance with a second clock signal different from the first clock signal, and the third logic element generates an output potential by inverting a polarity of the output potential of the second logic element.