Capacitor Mesh Compute-in-Memory for Low-Latency MAC
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Solution Overview
Problem
Data movement between processor and memory in traditional computing systems presents a significant performance and energy bottleneck, particularly in applications like machine learning, due to the separation of data storage and computational tasks.
Innovation Solution
An apparatus comprising a capacitor mesh circuit and a bitcell array, where each bitcell stores a weight bit and multiplies it by an input bit, with the output coupled to a capacitor mesh forming a binary-weighted capacitive voltage divider, enabling partial multiply-accumulate operations and accumulating results in a sample-and-hold circuit for analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is stored in separate memory and processed by a separate processor, then data storage and computational tasks are clearly separated, but data movement between processor and memory becomes a significant performance and energy bottleneck
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Bitcells that traditionally only store data are enhanced with multiplication units that can perform arithmetic operations directly within the memory array, eliminating the need to move data between separate memory and processor components.
Solution Approach 2:
The bitcell structure is designed to serve multiple functions: it can store weight bits in its storage unit and simultaneously perform multiplication operations with input bits through its multiplication unit. This multi-functional design allows the same hardware structure to handle both data storage and data processing tasks.
2Device complexity
If data is stored in separate memory and processed by a separate processor, then functional separation is maintained, but energy consumption increases due to data movement
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Bitcells that traditionally only store data are enhanced with multiplication units that can perform arithmetic operations directly within the memory array, eliminating the need to move data between separate memory and processor components.
3Ease of manufacture
If traditional separate memory and processor architecture is used, then modular design is simplified, but computational latency increases
Solution Approach 1:
The patent merges memory storage and computational processing into a single integrated structure. Bitcells that traditionally only store data are enhanced with multiplication units that can perform arithmetic operations directly within the memory array, eliminating the need to move data between separate memory and processor components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces computational latency and energy consumption by performing arithmetic operations directly in memory, enhancing processing performance and efficiency in tasks like convolutional functions and machine learning algorithms.
Implementation Method 1
each signal line in the plurality of signal lines is electrically coupled such that the capacitor mesh circuit forms a binary-weighted capacitive voltage divider circuit between the plurality of signal lines
Implementation Method 2
the output of each bitcell in a column of the bitcell array is coupled to corresponding signal line in the capacitor mesh circuit via at least one capacitor
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
According to an example embodiment, an apparatus comprises a capacitor mesh circuit comprising a plurality of signal lines and a bitcell array comprising a plurality of bitcells.