Capacitor Mismatch Measurement Circuit with Constant Drain Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for measuring capacitor mismatch in integrated circuits, particularly in high-performance devices like ADCs, suffer from inaccuracies due to parasitic capacitance effects and threshold voltage modulation, which are incompatible with precision circuits.
Innovation Solution
A circuit and method that maintains the drain-to-source voltage of a source follower transistor constant while ramping the voltage applied to a capacitor voltage divider, preventing parasitic capacitance effects and threshold voltage shifts, allowing for accurate measurement of capacitance ratios between capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement circuits are used to measure capacitor mismatch, then the measurement can be performed with simple circuitry, but parasitic capacitance effects and threshold voltage modulation cause measurement inaccuracies
Solution Approach 1:
The patent applies dynamics by making the drain voltage time-varying (ramping) rather than static, and by dynamically adjusting it to track the input voltage changes. This dynamic operation maintains constant drain-to-source voltage across the source follower during measurement, eliminating parasitic capacitance effects and threshold voltage modulation while preserving measurement accuracy.
Solution Approach 2:
The patent introduces an intermediary control voltage applied to the drain of the source follower transistor. This intermediary voltage acts as a mediator that compensates for the varying input voltage, maintaining a constant potential difference across the transistor and thereby eliminating the harmful parasitic effects without requiring complex additional circuitry.
2Measurement precision
If the voltage applied to the capacitor voltage divider is ramped to measure capacitance ratios, then capacitance measurements can be performed, but threshold voltage modulation and parasitic capacitance effects introduce non-linearities and measurement errors
Solution Approach 1:
The patent applies preliminary anti-action by preemptively counteracting the harmful parasitic capacitance effects and threshold voltage modulation through dynamic drain voltage adjustment. By ramping the drain voltage in conjunction with the input voltage, the method prevents these harmful effects from manifesting during the measurement process, thereby maintaining high measurement precision.
Solution Approach 2:
The patent changes the voltage parameter at the drain of the source follower from a static value to a dynamically varying value that tracks the input voltage. This parameter change transforms the operating conditions of the transistor, eliminating the non-linearities caused by parasitic capacitance and threshold voltage modulation while enabling accurate capacitance ratio measurements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides precise capacitance ratio measurements, reducing non-linearities and improving measurement accuracy, making it suitable for high-performance integrated circuits without requiring changes in testing methodology or circuit design.
Implementation Method 1
parasitic capacitance effects and threshold voltage modulation
Implementation Method 2
threshold voltage modulation
Data Source
AI summary
Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected to the gate of a source follower transistor. In one disclosed embodiment of the invention, a ramped voltage is applied to the drain of the source follower transistor simultaneously with the ramped voltage applied to the voltage divider; the slope of the ramped drain voltage is at the nominal slope of the voltage at the common node of the voltage divider. In another embodiment, a second transistor in saturation has its gate coupled to the source of the source follower device, and its source connected to the drain of the source follower device in series with a constant voltage drop. The drain-to-source voltage of the source follower device is thus held constant in each embodiment, improving precision of the measurement.