Package Decoupling Capacitor Mount Array Design
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Solution Overview
Problem
The existing integrated circuit packages face issues with long electrical paths and high impedance in decoupling capacitors, leading to inadequate power supply and excessive power supply noise, which affects signal integrity and reliability.
Innovation Solution
A package design with a mount array and substrate body featuring short electrical paths, low impedance, and low loop inductance, where the capacitor's electrical path is optimized by direct connections between conductive layers and terminal mounts, reducing loop inductance and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor is connected through multiple conductive layers with vias, then the capacitor can be integrated into the package structure, but the electrical path becomes long and impedance increases
Solution Approach 1:
The patent merges the capacitor's electrical connection directly with the terminal bumps by making the capacitor pads co-located with the terminal bumps. This eliminates the need for separate via connections through multiple conductive layers, thereby shortening the electrical path while maintaining reliable power supply stability.
Solution Approach 2:
The patent transitions from a vertical connection approach (through multiple conductive layers and vias) to a horizontal/planar connection approach where the capacitor pads are positioned at the same level as the terminal bumps. This dimensional change eliminates the need for deep via connections and reduces the overall electrical path length.
2Device complexity
If the capacitor electrical path is long and has high impedance, then the package structure can accommodate multiple layers, but power supply noise increases and decoupling effectiveness decreases
Solution Approach 1:
The patent extracts the capacitor connection from the multi-layer conductive structure and places it directly at the terminal bump level. This separation of the capacitor connection path from the internal conductive layers eliminates the high-impedance via paths that generate power supply noise, while the package can still maintain its multi-layer structure for other functions.
3Reliability
If vias are used to connect conductive layers, then electrical connectivity is achieved, but loop inductance increases and reduces capacitor effectiveness
Solution Approach 1:
The patent merges the capacitor pads with the terminal bumps, eliminating the need for via connections. This direct connection approach maintains electrical connectivity while significantly reducing the loop inductance that would otherwise be introduced by via paths through multiple conductive layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively stabilizes voltage delivery to the integrated circuit, ensuring reliable power supply during sudden current changes and reducing electromagnetic compatibility issues.
Implementation Method 1
The decoupling capacitors 38P provide a local source of charge so that the current can be supplied quickly without allowing the voltage across the positive and negative terminals to dip suddenly
Data Source
AI summary
A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integrated circuit (212). The mount array (219) includes a plurality of positive terminal mounts (342), a plurality of negative terminal mounts (344), and a plurality of signal mounts (346). The substrate body (216A) includes a first conductive layer (220a), a second conductive layer (220b), and an insulating layer (222a) that is positioned between the first conductive layer (220a) and the second conductive layer (220b). The first conductive layer (220a) includes (i) a terminal portion (350) that is connected one of the terminal mounts (342) (344), and (ii) a signal portion (352) that is connected to the signal mounts (346). Further, the second conductive layer (220b) is directly connected to the other of the terminal mounts (344) (342). Additionally, the package (216) can include a capacitor (238) having a positive capacitor pad (556) and a negative capacitor pad (554). The electrical path of the capacitor (238) to the mount array (219) in the designs provided herein is relatively short, has relatively low impedance, and has a relatively low loop inductance.