Multilayer Capacitor Mounting Orientation for Acoustic Noise Reduction
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Solution Overview
Problem
Multilayer capacitors generate acoustic noise due to piezoelectric vibrations, which can be perceived as abnormal device malfunctions in quiet environments and degrade voice output quality, especially when these vibrations occur in the audible frequency range or higher frequencies, affecting IT and automotive industries.
Innovation Solution
A mounting strategy for multilayer capacitors on a board is developed, where the internal electrodes are stacked either horizontally or vertically based on a ratio of pad distance to capacitor length (Lp/Lc), optimizing acoustic noise reduction by ensuring the dielectric layer and internal electrodes are aligned accordingly, with Lp/Lc ≤ 1.35 for horizontal alignment and > 1.35 for vertical alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multilayer capacitor is mounted on a board, then electrical function is achieved, but acoustic noise is generated due to piezoelectric vibrations
Solution Approach 1:
The patent applies asymmetry by determining the mounting direction based on the aspect ratio (Lp/Lc) of the capacitor. When Lp/Lc ≤ 1.35, the capacitor is mounted with its length direction parallel to the board surface; when Lp/Lc > 1.35, it is mounted perpendicular to the board surface. This asymmetric mounting strategy optimizes acoustic noise reduction while maintaining electrical functionality.
Solution Approach 2:
The patent changes the mounting orientation parameter based on the capacitor's dimensional parameters. By calculating the ratio Lp/Lc and comparing it to the threshold value of 1.35, the system selects the optimal mounting direction (parallel or perpendicular) to minimize acoustic noise generation from piezoelectric vibrations.
2Object-generated harmful factors
If internal electrodes are stacked horizontally, then acoustic noise reduction is optimized for Lp/Lc ≤ 1.35, but vertical stacking would be more space-efficient
Solution Approach 1:
The patent changes the mounting orientation parameter based on the capacitor's dimensional parameters. By calculating the ratio Lp/Lc and comparing it to the threshold value of 1.35, the system selects the optimal mounting direction (parallel or perpendicular) to minimize acoustic noise generation from piezoelectric vibrations.
Solution Approach 2:
The patent applies asymmetry by determining the mounting direction based on the aspect ratio (Lp/Lc) of the capacitor. When Lp/Lc ≤ 1.35, the capacitor is mounted with its length direction parallel to the board surface; when Lp/Lc > 1.35, it is mounted perpendicular to the board surface. This asymmetric mounting strategy optimizes acoustic noise reduction while maintaining electrical functionality.
3Object-generated harmful factors
If internal electrodes are stacked vertically, then acoustic noise reduction is optimized for Lp/Lc > 1.35, but horizontal stacking would be more space-efficient
Solution Approach 1:
The patent changes the mounting orientation parameter based on the capacitor's dimensional parameters. By calculating the ratio Lp/Lc and comparing it to the threshold value of 1.35, the system selects the optimal mounting direction (parallel or perpendicular) to minimize acoustic noise generation from piezoelectric vibrations.
Solution Approach 2:
The patent applies asymmetry by determining the mounting direction based on the aspect ratio (Lp/Lc) of the capacitor. When Lp/Lc ≤ 1.35, the capacitor is mounted with its length direction parallel to the board surface; when Lp/Lc > 1.35, it is mounted perpendicular to the board surface. This asymmetric mounting strategy optimizes acoustic noise reduction while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reverses and optimizes acoustic noise reduction in both audible and high-frequency ranges, improving device performance and user experience by selectively mounting capacitors to minimize noise, as demonstrated by experiments showing reduced acoustic noise levels.
Implementation Method 1
As the dielectric material has piezoelectricity, the dielectric material may be synchronized with an applied voltage and may be deformed.
Data Source
AI summary
An electronic component includes a board having first and second electrode pads on one surface of the board; and a multilayer capacitor. The multilayer capacitor comprises: a capacitor body comprising a dielectric layer and a plurality of internal electrodes, disposed horizontally with respect to a mounting surface of the capacitor body facing the one surface of the board, and external electrodes disposed on both end portions of the capacitor body and connected to exposed portions of the internal electrodes, respectively. The electronic component satisfies Lp/Lc≤1.35, where a distance between outer edges of the first and second electrode pads is defined as Lp, and a length of the multilayer capacitor is defined as Lc.