Multilayer Substrate Capacitor Mounting Structure for ESL Reduction
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Solution Overview
Problem
Conventional electronic component mounting structures face challenges in space saving and increased ESL due to densely arranged capacitors with different capacitances, particularly when high-capacity capacitors are involved, leading to enhanced magnetic flux and mutual inductance issues.
Innovation Solution
The proposed electronic component mounting structure features a first capacitor with higher capacitance and a second capacitor with lower capacitance, arranged in a two-tier structure on a multilayer substrate, where the second capacitor overlaps the first and is electrically connected to the substrate's surface-mounted electrode parts, allowing currents to flow parallel and opposite each other, thereby canceling magnetic flux and reducing ESL through polarity differences in through-hole conductor parts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If capacitors with different capacitances are arranged two-dimensionally on the multilayer substrate, then the space utilization is improved, but the ESL increases due to enhanced mutual inductance between components
Solution Approach 1:
The patent transitions from traditional two-dimensional planar arrangement of capacitors to a three-dimensional stacked configuration where capacitors are arranged in multiple layers vertically on the multilayer substrate. This dimensional change allows capacitors to be positioned at different heights (Z-axis) while maintaining compact footprint, thereby reducing mutual inductance between adjacent capacitors and lowering ESL without sacrificing space utilization
Solution Approach 2:
The patent segments the capacitor arrangement into multiple independent layers or tiers on the multilayer substrate. By dividing the single-layer arrangement into multiple segments stacked vertically, the design reduces the density of capacitors in any single plane, thereby minimizing mutual inductance effects while maintaining high overall capacitance density through the three-dimensional structure
2Quantity of substance
If high-capacity capacitors with large size are used, then the required capacitance is achieved, but the space consumption increases significantly
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple capacitor layers on the multilayer substrate. This allows the system to achieve high total capacitance capacity by combining smaller capacitors in series and parallel configurations across multiple layers, rather than relying on a single large high-capacity capacitor, thereby significantly reducing the footprint area required
Solution Approach 2:
The patent implements a nested arrangement where multiple capacitor structures are integrated within the vertical profile of the multilayer substrate. Smaller capacitors are positioned in nested configurations within the available vertical space, maximizing the use of three-dimensional volume to achieve high capacitance density without increasing the planar mounting area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves package density without densely arranging components, effectively reducing ESL while conserving space by increasing the number of through-hole conductor parts and capacitors that cancel magnetic flux, thus enhancing the ESL reduction effect.
Implementation Method 1
currents flowing through the first capacitor and currents flowing through the second capacitor are directed parallel to each other, so that their mutual inductance allows magnetic fluxes to cancel each other out, thereby reducing the ESL
Data Source
AI summary
An electronic component mounting structure which can reduce the ESL while saving the space when mounting electronic components is provided. A first electronic component 7 is electrically connected to surface-mounted electrode parts 11A, 12A at metal terminals 26, 27 such that a first capacitor 24 having a greater capacitance and a mounting surface 4a of a multilayer substrate 4 are separated from each other. A second electronic component 8 is arranged between the first capacitor 24 and the mounting surface 4a and electrically connected to surface-mounted electrode parts 12B, 11B at second terminal electrodes 32, 33. The second electronic component 8 overlaps the first capacitor 24 when seen in the laminating direction. The first electronic component 7 is mounted to the multilayer substrate 4 such that first terminal electrodes 22, 23 oppose each other in a predetermined direction D1. The second electronic component 8 is mounted to the multilayer substrate 4 such that the second terminal electrodes 32, 33 oppose each other in the predetermined direction D1.