Capacitor Mounting Inductance Reduction via Multi-Via Patterns
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Solution Overview
Problem
High mounting inductance associated with decoupling capacitors on circuit boards limits performance and often requires more costly capacitors to achieve target performance, and there is a need to enhance the self-resonant frequency range of these capacitors.
Innovation Solution
A circuit board design featuring a mounting pad with a specific pattern of holes for receiving conductive material to create vias, which reduces mounting inductance and includes a through via connecting top and bottom capacitors to internal conductive layers, allowing for different self-inductances and a broader self-resonant frequency range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single vias are used for coupling decoupling capacitors to circuit board terminals, then the mounting structure is simple, but mounting inductance is high which limits performance
Solution Approach 1:
The patent divides the single via connection into multiple vias (first via and second via) that are spatially separated and connect to different terminals of the decoupling capacitor. This segmentation reduces the inductance of each individual via connection while maintaining structural simplicity.
Solution Approach 2:
The patent transitions from a single-point via connection to a distributed multi-point connection pattern. By arranging vias in different spatial locations and connecting them to different capacitor terminals, the solution adds spatial dimensionality to reduce inductance without significantly increasing structural complexity.
2Reliability
If more costly capacitors are used, then target performance can be achieved, but component cost increases
Solution Approach 1:
The patent changes the mounting inductance parameter by using multiple vias with different lengths and configurations (first via extending from first surface, second via extending from second surface). This allows standard capacitors to achieve target performance by optimizing the mounting structure rather than requiring expensive specialized capacitors.
3Reliability
If decoupling capacitors are mounted on both top and bottom sides of circuit board, then capacitance coverage is improved, but mounting inductance remains significant without common via coupling
Solution Approach 1:
The patent merges the mounting structures of top and bottom side capacitors by using a common via that extends through the entire circuit board. This common via electrically connects the capacitors on both surfaces, reducing overall mounting inductance while maintaining the dual-side capacitance coverage.
Solution Approach 2:
The common via acts as an intermediary element that connects the decoupling capacitors mounted on opposite sides of the circuit board. This intermediary structure enables electrical coupling between the capacitors and reduces the total inductance of the decoupling network.
Data Source
AI summary
Reduced mounting inductance and/or an increased self-resonant frequency range of operation for capacitor circuits of a circuit board is described. The circuit board has a mounting pad for coupling a capacitor to at least three vias arranged in a pattern and coupled to the mounting pad at least three discrete locations to reduce mounting pad inductance. Alternatively or additionally, top and bottom mounted capacitors to the circuit board have a physically and electrically common through via to provide a self-resonant frequency range of operation.