Capacitor Multiplier Circuit for CMOS Image Sensor Noise Attenuation
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Solution Overview
Problem
In CMOS image sensor devices, the need for large capacitors to attenuate row-wise temporal noise is hindered by fabrication costs and limited space, as existing capacitor structures, such as polysilicon-to-polysilicon or metal-to-metal layers, result in low capacitance density, making it costly to implement effective noise filtering.
Innovation Solution
The implementation of capacitor multiplier circuits that utilize a common current multiplier circuit to create a large effective capacitance from a small on-chip capacitor, using NMOS and PMOS transistors with specific aspect ratios to amplify current and achieve a higher capacitance value, effectively filtering row-wise temporal noise by coupling the capacitor multiplier circuit between the VLN line and ground.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large capacitor is implemented using conventional polysilicon-to-polysilicon or metal-to-metal structures, then noise attenuation performance is improved, but fabrication cost and device area increase significantly
Solution Approach 1:
The patent changes the fundamental parameter of capacitance density by transitioning from conventional polysilicon-to-polysilicon or metal-to-metal capacitor structures (with capacitance density of a few fF/μm2) to a capacitor multiplier circuit implementation that achieves effectively higher capacitance values without proportional area increase. This parameter change enables large effective capacitance (hundreds of pF to nF range) to be realized within acceptable area constraints.
Solution Approach 2:
The patent creates an effective copy of a large capacitor's electrical behavior using a capacitor multiplier circuit. Instead of physically implementing a large capacitor with proportionally large area, the circuit replicates the electrical characteristics of a large capacitor through transistor-based current multiplication, achieving the same noise filtering effect without the physical footprint of a conventional large capacitor.
2Reliability
If capacitor size is increased to attenuate row-wise temporal noise, then noise filtering capability is improved, but available die area is consumed
Solution Approach 1:
The patent transforms the area-capacitance relationship by implementing a capacitor multiplier circuit that decouples effective capacitance value from physical area. The circuit uses transistor aspect ratios and current multiplication to achieve effectively higher capacitance values without proportional area increase, enabling noise attenuation while preserving die area for other functions.
Solution Approach 2:
The patent introduces a new dimensional approach by using the transistor current gain dimension (β) to multiply capacitance effect. Instead of increasing capacitance through physical area expansion in two dimensions, the circuit exploits the current multiplication dimension provided by transistor gain, effectively projecting capacitance enhancement into a different operational dimension.
3Quantity of substance
If polysilicon-to-polysilicon capacitor structure is used, then capacitance density is improved, but fabrication process complexity increases
Solution Approach 1:
The patent replicates the high capacitance density effect of polysilicon-to-polysilicon structures using a capacitor multiplier circuit built with standard CMOS transistors. Instead of requiring specialized polysilicon capacitor fabrication processes, the circuit copies the electrical behavior of high-density capacitors using readily available MOS transistor structures and their current multiplication properties.
Solution Approach 2:
The patent substitutes the physical mechanical structure of a large polysilicon capacitor with an electronic circuit implementation. Rather than relying on the physical proximity and material properties of polysilicon layers to achieve high capacitance density, the circuit uses electronic current multiplication through transistors to achieve the same electrical effect with standard CMOS processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective attenuation of row-wise temporal noise by creating a large capacitance that mimics a physically large capacitor, reducing noise in CMOS image sensors without the need for extensive fabrication modifications, thereby improving image quality by filtering low-frequency noise up to 1 MHz.
Implementation Method 1
utilize a common current multiplier circuit to create a large effective capacitance from a small on-chip capacitor, using NMOS and PMOS transistors to amplify current and achieve a higher capacitance value
Implementation Method 2
effectively filtering row-wise temporal noise in the range of 1 KHz to 1 MHz, reducing noise interference while minimizing physical size and fabrication costs
Data Source
AI summary
The various embodiments disclose capacitor multiplier circuits that may be integrated into imaging devices, such as for semiconductor Complimentary Metal Oxide Semiconductor (CMOS) image sensors, to create an effective capacitance in response to a low frequency, such as row-wise temporal noise, that may be generated along a row of image sensor pixels. The created effective capacitance from any one of the capacitor multiplier circuits along with a small signal resistance created by a trans-conductance of a current biasing transistor form a low pass filter that will attenuate the low frequency noise.