Capacitor Overvoltage Testing via Segmented Substrate Isolation
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Solution Overview
Problem
Conventional high voltage overvoltage stress testing (OVST) structures face challenges in isolating components within integrated circuits (ICs) from excessive stress, as components like transistors are subjected to full OVST voltage due to capacitors not being tied to the substrate potential, leading to potential functional problems.
Innovation Solution
The design includes a capacitor configuration with a substrate having specific conductivity type regions, dielectric and conductive layers, and a decoupler structure that allows the parasitic capacitor to be isolated during OVST, enabling application of negative voltage and safe stress up to 128V or greater by reverse biasing diodes formed between the epitaxial layer and well regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the capacitor is not tied to the substrate potential to enable high voltage operation, then the capacitor can achieve higher voltage rating, but other components in the IC are subjected to full OVST voltage causing functional problems
Solution Approach 1:
The substrate is segmented into multiple conductivity type regions (first region of first conductivity type, second region of second conductivity type, third region of second conductivity type) that are substantially surrounded by each other, creating isolated zones with different electrical characteristics. This segmentation allows the capacitor to operate at high voltage while other IC components remain protected at lower voltages.
Solution Approach 2:
Dielectric layers are introduced as intermediary elements between the conductive regions and the capacitor structure. These dielectric layers (formed over the substrate regions and between conductive layers) act as mediators that enable high voltage stress on the capacitor while preventing direct voltage transmission to other IC components, thus resolving the contradiction between high voltage rating and component protection.
2Measurement precision
If high voltage OVST is applied to the parasitic capacitor to accelerate latent defects, then defect detection capability is improved, but the capacitor and surrounding components are exposed to damaging voltage levels
Solution Approach 1:
The segmented substrate structure with alternating conductivity regions enables the parasitic capacitor to be isolated electrically from other IC components during OVST. This allows application of high voltage (e.g., 60% greater than capacitor voltage rating) to accelerate latent defects like cone defects in the dielectric layer, while the segmentation prevents this high stress from propagating to and damaging other components.
Solution Approach 2:
Different regions of the substrate are given different conductivity types and electrical characteristics tailored to specific functions. The regions surrounding the capacitor are designed with properties that enable high voltage tolerance, while other regions maintain normal operating characteristics. This local differentiation allows high voltage OVST to be applied locally to the capacitor without compromising overall IC reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively isolates the capacitor during OVST, allowing it to be safely stressed beyond its normal voltage rating without damaging other IC components, ensuring reliable testing and defect detection.
Implementation Method 1
enabling application of negative voltage and safe stress up to 128V or greater by reverse biasing diodes formed between the epitaxial layer and well regions
Data Source
AI summary
An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.