Capacitor Landing Pad Trench Layout to Prevent DRAM Shorts
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Solution Overview
Problem
As semiconductor devices are scaled down, the precision of photo mask alignment during the fabrication of capacitor landing pads becomes challenging, leading to adjacent landing pads connecting and causing short circuits in DRAMs.
Innovation Solution
A method involving the formation of a substrate with word lines, insulating layers, and a metal layer, where a series of pattern processes create third hard masks that define trenches for capacitor landing pads, ensuring the bottom of the trench is lower than the top surface of the insulating layers to prevent connections between pads, and a dielectric layer is used to fill the trenches, with the dielectric layer's bottom surface being lower than the bit line top surface to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photo mask alignment is used during landing pad fabrication, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates causing adjacent landing pads to connect and cause short circuits
Solution Approach 1:
The fabrication process is divided into multiple sequential pattern processes (first pattern process, second pattern process) with corresponding hard masks (first hard mask, second hard mask, third hard mask). Each pattern process creates progressively more precise patterns, segmenting the complex alignment task into manageable steps that achieve high precision without requiring advanced photo mask alignment technology.
Solution Approach 2:
The first hard mask is formed in advance to define initial patterns, which then serve as the basis for the second pattern process. The second hard mask is formed based on the first pattern, and the third hard mask is formed based on the second pattern. This preliminary action approach allows each subsequent step to build upon previous patterns, achieving cumulative precision improvement.
2Reliability
If trench depth is increased to separate landing pads, then short circuit prevention is improved, but manufacturing complexity increases
Solution Approach 1:
The trench is formed with specific local characteristics: the bottom of the trench is positioned at a precise depth below the top surface of the insulating layers, and the dielectric layer is filled to a specific level below the bit line top surface. This localized precision in trench depth and dielectric layer positioning provides effective electrical isolation without requiring excessive trench depth throughout the entire structure.
Solution Approach 2:
The dielectric layer serves as an intermediary material that fills the trench and provides electrical isolation between the capacitor landing pad and the bit line. By using this intermediate dielectric layer with controlled positioning, the patent achieves reliable isolation without requiring the trench to extend through the entire structure depth.
Data Source
AI summary
A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.