Semiconductor Capacitor Pad Layout for Void-Free Reflow Joints

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Solution Overview

Problem

The junction reliability of thin film capacitors in semiconductor packages is compromised due to the formation of large voids during the reflow process, caused by flux gas vaporization from solder paste, which affects the integrity of the capacitor joints.

Innovation Solution

The semiconductor package design incorporates capacitor pads with via patterns eccentric from the center line and a small diameter, allowing flux gas to escape easily, thereby preventing large void formation and enhancing junction reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder paste is used to mount the capacitor during reflow process, then the capacitor can be securely attached to the substrate, but flux gas vaporization forms large voids in the joint that deteriorate connection reliability

Engineering Contradiction:
Improveconnection reliabilityVSAvoidvoid formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The via pattern is positioned eccentrically (off-center) relative to the capacitor pad, creating an asymmetric configuration. This asymmetry provides an escape path for flux gas during reflow, preventing gas accumulation and large void formation in the joint, thereby resolving the contradiction between secure attachment and void-free bonding

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The via pattern acts as an intermediary structure between the capacitor pad and the substrate. It serves dual functions: providing electrical connection and creating a controlled pathway for flux gas escape, thus mediating between the bonding process requirements and the void formation problem

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the via pattern is positioned at the center of the capacitor pad, then the electrical connection is optimized, but flux gas gets trapped and forms large voids

Engineering Contradiction:
Improvejoint integrityVSAvoidgas trapping
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The via pattern is deliberately positioned asymmetrically (eccentrically) rather than at the center of the capacitor pad. This asymmetric positioning creates an escape route for flux gas during reflow, preventing gas trapping and large void formation while maintaining adequate electrical connection through the via

Inventive Principle:
Principle #4Asymmetry

3Reliability

If a large diameter via pattern is used, then the electrical connection area is increased, but the flux gas escape path is blocked leading to void formation

Engineering Contradiction:
Improveelectrical connectionVSAvoidvoid growth
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The via pattern uses a controlled diameter that is optimized to balance electrical connection requirements with flux gas escape needs. The eccentric positioning ensures that even with a substantial via diameter for good electrical connection, there remains sufficient space around the via for flux gas to escape, preventing void growth

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively mitigates void growth and improves the reliability of capacitor joints by allowing flux gas to escape, ensuring better electrical connections and package integrity.

Implementation Method 1

The via pattern may be eccentric by a distance from a center line of the pad pattern... allowing flux gas to escape easily, thereby preventing large void formation and enhancing junction reliability

Methodology Applied
Scientific EffectGas escape through via pattern:

Data Source

PatentUS11824033B2Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2023.11.21 SAMSUNG ELECTRONICS CO LTD
  • US11824033B2 patent drawing
  • US11824033B2 patent drawing
  • US11824033B2 patent drawing

AI summary

A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.