Capacitor-Incorporated PCB Underfill Stress Relief
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Solution Overview
Problem
Conventional built-up multilayered printed wiring boards incorporating capacitors with ceramic high dielectric layers face issues such as cracking due to thermal expansion coefficient differences and humidity-induced leakage, leading to reduced insulation reliability and decoupling effectiveness.
Innovation Solution
A capacitor-incorporated printed wiring board design featuring a ceramic high dielectric layer sandwiched between electrodes, with a larger underfill resin area covering the capacitor to reduce stress and prevent cracking, and a semiconductor device mounting pad configuration that minimizes warp and deformation, using specific materials like barium titanate and copper/nickel electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a ceramic high dielectric layer is used in the capacitor, then the decoupling effectiveness is improved, but the layer is prone to cracking due to thermal expansion coefficient differences
Solution Approach 1:
The patent applies different materials with different properties to different regions: the ceramic high dielectric layer (barium titanate) is used locally in the capacitor portion where high decoupling effectiveness is needed, while the surrounding wiring board uses a different ceramic composition with thermal expansion coefficient matched to the substrate. This local differentiation allows the capacitor to maintain high performance without the entire board being susceptible to thermal cracking.
Solution Approach 2:
The patent uses composite ceramic materials: the capacitor dielectric layer is made of barium titanate (BaTiO3) for high permittivity, while the wiring board ceramic is a composite formulation (containing alumina, silica, and other oxides) designed to match the thermal expansion coefficient of the substrate. This composite approach allows simultaneous achievement of electrical performance and thermal stability.
2Reliability
If the capacitor structure is incorporated into the printed wiring board, then the decoupling effect is enhanced, but humidity-induced leakage occurs reducing insulation reliability
Solution Approach 1:
The patent introduces an underfill resin as an intermediary material that fills the space between the capacitor electrodes and the substrate. This underfill resin acts as a barrier that prevents humidity from reaching the capacitor electrodes, thereby eliminating the humidity-induced leakage path while allowing the capacitor to maintain its decoupling function.
Solution Approach 2:
The patent uses a sacrificial organic material (underfill resin) that provides temporary protection during operation. This material is designed to be stable under normal operating conditions, preventing humidity ingress, but can be replaced or degraded if needed. The underfill resin serves as a cost-effective solution to protect the expensive capacitor structure.
3Strength
If the underfill covered area is made larger to cover the capacitor, then crack prevention is improved, but the device complexity increases
Solution Approach 1:
The patent merges the underfill resin function with the existing capacitor structure by making the underfill covered area extend beyond the capacitor boundaries to include surrounding regions. This unified approach allows the single underfill material to simultaneously protect both the capacitor from cracking and the surrounding wiring board from humidity, simplifying the overall protection scheme while reducing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances insulation reliability and decoupling performance by preventing cracks in the high dielectric layer and maintaining a sufficient decoupling effect even at high frequencies, ensuring stable operation of semiconductor devices.
Implementation Method 1
a larger underfill resin area covering the capacitor to reduce stress and prevent cracking
Implementation Method 2
a capacitor having a ceramic high dielectric layer sandwiched by a first electrode and a second electrode
Implementation Method 3
ceramic high dielectric layer
Data Source
AI summary
A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer being interposed between a first and a second electrode, and a semiconductor device mounting pad, including a first and a second pad, formed on an outermost resin insulating layer of the resin insulating layers. An underfill which covers an area larger than that of the high dielectric layer is formed, when the underfill covered area is projected along a lamination direction of the resin insulating layers to a face on which the high dielectric layer is formed. The capacitor is located immediately beneath the underfill covered area.