Capacitor-Based Phase Interpolation Circuit for Better Linearity

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Solution Overview

Problem

Conventional phase interpolation circuits have complex structures, poor linearity, high power consumption, and longer signal delays.

Innovation Solution

A phase interpolation circuit utilizing a capacitor and multiple charging and discharging circuits with weighting control codes to generate a phase interpolation signal, featuring a simple circuit design that improves linearity and reduces power consumption and signal delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional phase interpolation circuits are used, then phase interpolation function is achieved, but circuit structure becomes complex

Engineering Contradiction:
Improvecircuit structureVSAvoidlinearity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The phase interpolation function is segmented into multiple independent charging and discharging circuits, each handling specific phase intervals. This segmentation simplifies the overall circuit structure while maintaining interpolation accuracy, as each circuit module operates independently with controlled switching based on phase selection signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple charging and discharging circuits are designed with identical circuit topologies that can be universally applied across different phase interpolation ranges. This universal design reduces circuit complexity by using repeated modular structures rather than unique circuits for each phase interval, while still achieving comprehensive phase coverage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If conventional phase interpolation circuits are used, then phase interpolation function is achieved, but power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidlinearity
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The circuit employs periodic charging and discharging actions synchronized with the clock signal phases. By activating specific charging/discharging circuits only during their designated phase intervals and keeping others inactive, power consumption is reduced while maintaining continuous phase interpolation functionality across all phases through this periodic activation pattern.

Inventive Principle:
Principle #19Periodic action

3Loss of time

If conventional phase interpolation circuits are used, then phase interpolation function is achieved, but signal delay increases

Engineering Contradiction:
Improvesignal delayVSAvoidlinearity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The charging and discharging circuits are pre-configured with switching elements that can be rapidly activated based on phase selection signals. This preliminary configuration allows the circuit to immediately switch between different charging/discharging paths without requiring complex real-time calculations or adjustments, thereby reducing signal delay while maintaining accurate phase interpolation.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed circuit enhances linearity and reduces power consumption and signal delay while maintaining efficient phase interpolation.

Implementation Method 1

a capacitor; a first charging circuit, coupled to the capacitor, configured to selectively charge the capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20250379569A1Phase interpolation circuit
Publication Date: 2025.12.11 REALTEK SEMICON CORP
  • US20250379569A1 patent drawing
  • US20250379569A1 patent drawing
  • US20250379569A1 patent drawing

AI summary

A phase interpolation circuit for generating a phase interpolation signal, comprising: a capacitor; a first charging circuit for selectively charging the capacitor according to a first clock signal and a first weighting control code; a second charging circuit for selectively charging the capacitor according to a second clock signal and a second weighting control code; a first discharge circuit for selectively discharging the capacitor according to the first clock signal and a third weighting control code; and a second discharge circuit for selectively discharging the capacitor according to the second clock signal and a fourth weighting control code. The first, second, third and fourth weighting control codes respectively control the weightings of the first clock signal and the second clock signal in the phase interpolation signal.