Capacitor Pillars in 3D Memory for Area Scaling
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Solution Overview
Problem
Three-dimensional memory devices face challenges in scaling and efficient chip area utilization due to the large area required by capacitors with high capacitance, which impede device miniaturization and performance.
Innovation Solution
The development of semiconductor structures with capacitor pillars that include a node dielectric and semiconductor material portions, where the semiconductor material portions are laterally surrounded by the node dielectric, and electrically conductive strips that form electrodes, allowing for high-capacity capacitors within a compact footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional two-dimensional memory structures are used, then device area utilization is limited, but capacitor area requirements increase device footprint
Solution Approach 1:
The patent transitions from two-dimensional memory layouts to three-dimensional structures by forming vertical capacitor pillars that extend through alternating stacks of insulating and conductive layers. This vertical integration allows capacitors to be stacked above memory regions, effectively utilizing the third dimension (height) to reduce the horizontal chip area footprint while maintaining high capacitance values through the multi-layer stacked architecture
2Quantity of substance
If capacitor size is reduced to improve scaling, then capacitance value decreases, but device area can be reduced
Solution Approach 1:
The patent implements nested capacitor structures where multiple electrode layers and dielectric layers are stacked concentrically within vertical pillar regions. The capacitor pillars contain nested alternating stacks of conductive electrodes and insulating dielectrics, with each layer contributing to the total capacitance. This nested multi-layer approach enables high capacitance values to be achieved within compact vertical footprints, as the capacitance accumulates through the series of nested layers rather than requiring large lateral expansion
Solution Approach 2:
The patent employs composite material structures combining multiple conductive materials (such as doped polysilicon, metal layers) and insulating dielectric materials (such as silicon oxide, silicon nitride) in alternating stacks to form capacitor pillars. These composite structures optimize the capacitance-to-area ratio by selecting materials with high dielectric constants and appropriate conductivity, enabling high-capacity capacitors in reduced areas through superior material properties rather than increased physical size
Data Source
AI summary
A semiconductor structure can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and capacitor pillar structures vertically extending through the first alternating stack. Each of the capacitor pillar structures can include a node dielectric and a semiconductor material portion that is laterally surrounded by the node dielectric. A first electrode layer of a capacitor includes the semiconductor material portions, and a second electrode layer of the capacitor includes the electrically conductive layers. Alternatively or additionally, a first dielectric fill material portion can extend through the alternating stack and can include a plurality of capacitor via cavities. A capacitor can be provided within the plurality of capacitor via cavities.