Capacitor Profile Control via Ion Reflecting Mask
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Solution Overview
Problem
The challenge in semiconductor storage devices is controlling the bowing effect during the etching of deep trenches for vertical capacitors, which leads to enlarged trench diameters and potential electrical shorts due to the high aspect ratio of the trenches, causing issues with capacitance and device performance.
Innovation Solution
A method involving the use of an ion reflecting mask layer with specific thickness and etching processes, including the application of plasma ions through patterned openings to form trenching capacitor profiles with controlled bowing profiles at 75%-95% of the trench height, reducing the maximum diameter of the bowing profile to less than or equal to 1.2 times the trench diameter, thereby minimizing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the aspect ratio of the trench is increased to reduce capacitor area and increase capacitance, then the occupied chip area is reduced and capacitance is increased, but the sidewalls of the trench bear strong plasma collisions causing over-etching and bowing effect that enlarges trench diameters
Solution Approach 1:
A sacrificial layer is formed at the bottom of the trench before the main etching process. This sacrificial layer serves as a protective barrier during etching, preventing excessive ion bombardment damage to the trench sidewalls and reducing the bowing effect. The sacrificial layer is removed after etching is complete, leaving a trench with better profile control.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the etching plasma and the trench bottom. It absorbs some of the plasma ion energy and protects the actual trench structure from direct damage, thereby reducing over-etching and bowing while allowing the high aspect ratio etching to proceed.
2Productivity
If the opening size of the trenches is reduced to achieve larger aspect ratio, then the capacitance per unit area is increased, but the bowing effect becomes more severe leading to adjacent trenches merging and electrical shorts
Solution Approach 1:
The sacrificial layer is deposited at the trench bottom before etching begins. During the etching process, this layer protects the trench sidewalls from excessive ion bombardment that would otherwise cause severe bowing and merging of adjacent trenches. After etching, the sacrificial layer is removed, leaving well-defined separated trenches.
Solution Approach 2:
The sacrificial layer provides preliminary protection against the harmful bowing effect before it can cause trench merging. By being in place during etching, it counteracts the tendency of plasma ions to enlarge the trench diameter, thereby preventing electrical shorts between adjacent capacitors.
3Quantity of substance
If deep trenches are etched to form vertical capacitors, then the capacitance is increased without increasing chip area, but the plasma collisions on sidewalls cause over-etching that enlarges trench diameters
Solution Approach 1:
The sacrificial layer is formed at the trench bottom prior to the main etching process. This layer serves as a protective barrier that reduces plasma ion bombardment damage to the trench sidewalls during deep trench etching, thereby maintaining better diameter control while achieving the desired deep trench structure for high capacitance.
Solution Approach 2:
The sacrificial layer acts as a mediator between the high-energy plasma ions and the trench sidewalls during deep etching. It absorbs excess ion energy and prevents direct damage to the trench structure, enabling deep trench formation with controlled dimensions and high capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more vertical capacitor profile, reducing the occurrence of electrical shorts and enhancing the performance of semiconductor storage devices by maintaining a controlled bowing effect and preventing adjacent capacitors from merging.
Implementation Method 1
forming a plurality of trenching capacitor profiles by etching through the dielectric layer from the plurality of patterned openings, respectively, to expose the semiconductor substrate. Each trenching capacitor profile may include a bowing profile formed at 75%-95% of a height of the trenching capacitor profile above the semiconductor substrate.
Implementation Method 2
applying plasma ions through the plurality of patterned openings; and forming the bowing profiles by reflected plasma ions via sidewalls of the plurality of patterned openings.
Data Source
AI summary
A method for forming a capacitor profile on a semiconductor is disclosed. The method includes: providing a semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming an ion reflecting mask layer on the dielectric layer; forming a plurality of patterned openings by etching through the ion reflecting mask layer to expose the dielectric layer; and forming a plurality of trenching capacitor profiles by etching through the dielectric layer from the plurality of patterned openings, respectively, to expose the semiconductor substrate. Each trenching capacitor profile includes a bowing profile formed at 75%-95% of a height of the trenching capacitor profile above the semiconductor substrate.