Capacitor Randomization for CMOS Image Sensor VFPN Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CMOS image sensors face challenges with vertical fixed pattern noise (VFPN) due to capacitor mismatch, which increases under bright conditions and is difficult to address without increasing capacitor size, affecting both area and speed, and thus, cost and frame rate.
Innovation Solution
Implementing a readout circuit with capacitor randomization, where the connections to capacitors are changed randomly to set the gain, reducing the impact of capacitor mismatch and thereby minimizing VFPN, while maintaining desired gain levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor size is increased to reduce capacitor mismatch and VFPN, then manufacturing precision improves, but area increases and speed decreases
Solution Approach 1:
The patent applies dynamics by randomly switching capacitor connections row-by-row during operation. Instead of using fixed large capacitors, the system dynamically reconfigures which capacitors are connected to which columns, allowing smaller capacitors to achieve the same noise reduction effect through temporal variation in connectivity patterns.
Solution Approach 2:
The patent changes the connectivity parameters of capacitors randomly for each row. By varying which capacitors are connected to which column circuits in a random pattern, the system achieves averaging of capacitor mismatch effects without requiring larger capacitor sizes, thus reducing VFPN while maintaining compact area.
2Manufacturing precision
If capacitor size is increased to reduce capacitor mismatch and VFPN, then manufacturing precision improves, but speed decreases
Solution Approach 1:
The patent uses dynamic random switching of capacitor connections on a row-by-row basis, enabling the system to process multiple rows simultaneously with different capacitor configurations. This dynamic approach avoids the speed penalty of larger capacitors while maintaining noise reduction performance through temporal averaging of mismatch effects.
Solution Approach 2:
The patent segments the capacitor array into multiple smaller capacitors that can be independently connected to different columns. By dividing the total capacitance into smaller units and randomly assigning connections, the system achieves the same noise reduction as a single large capacitor but with faster switching and smaller individual capacitor sizes.
3Device complexity
If capacitor connections are fixed to provide stable gain, then device complexity reduces, but VFPN increases under bright conditions
Solution Approach 1:
The patent introduces dynamic random switching of capacitor connections controlled by a random number generator. This adds complexity to the connection configuration but eliminates VFPN by ensuring that no single capacitor mismatch pattern consistently affects the same column, thereby averaging out the noise across multiple rows.
Solution Approach 2:
The patent introduces a random number generator and switching circuitry as intermediaries between the fixed capacitor array and the column circuits. These intermediary components randomly reconfigure the connections, preventing direct mapping of capacitor mismatches to specific columns and thus reducing VFPN while maintaining manageable overall system complexity.
Data Source
AI summary
A pixel cell readout circuit includes a bitline input stage coupled to a bitline to receive an image signal from a pixel cell. A capacitor ratio circuit is coupled to the bitline input stage. A gain of the bitline input stage is responsive to a capacitor ratio provided by the capacitor ratio circuit to the bitline input stage. A switch control circuit is coupled to receive a gain signal. The switch control circuit is coupled to generate a randomized pattern selection signal coupled to be received by the capacitor ratio circuit to select the capacitor ratio provided by the capacitor ratio circuit in response to the gain signal.