Capacitor Structure with Recessed Electrode for DRAM
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Solution Overview
Problem
As semiconductor process technology advances, the miniaturization of DRAM capacitors leads to misalignment and overlay errors during lithography, resulting in insufficient process windows for etching high aspect ratio openings, which affects the formation of efficient capacitor structures.
Innovation Solution
A capacitor structure with a cylindrical lower electrode featuring a recessed bottom portion that extends to the sidewall of the storage node pad, formed through a method involving multiple etching processes and a lattice layer to ensure precise etching and increased contact area, using different etching gases and anisotropic etching to achieve a bottle-shaped design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the capacitor size is reduced to minimize chip area, then the chip area occupied by each capacitor is reduced, but the process window for etching high aspect ratio openings becomes insufficient due to misalignment and overlay errors
Solution Approach 1:
The etching process is divided into multiple stages with different etching gases. The first etching process uses a first etching gas to etch the initial opening, and the second etching process uses a second etching gas to etch the high aspect ratio opening. This segmentation allows each etching stage to be optimized for its specific requirements, improving the overall process window.
Solution Approach 2:
The patent changes the etching gas parameter between two different etching processes. The first etching gas and second etching gas have different properties that are optimized for different stages of opening formation. This parameter change enables precise control over the etching process, maintaining adequate process window even as capacitor dimensions are reduced.
2Productivity
If high aspect ratio openings are etched to achieve miniaturized capacitors, then the capacitor density is improved, but misalignment and overlay errors increase
Solution Approach 1:
The formation of high aspect ratio openings is segmented into two etching processes. The first process creates an initial opening with adequate margins, and the second process completes the high aspect ratio opening. This segmentation reduces the cumulative alignment errors that would occur in a single etching step.
Solution Approach 2:
The first etching gas and second etching gas act as intermediaries that facilitate the stepwise formation of high aspect ratio openings. Each gas is selected to optimize specific aspects of the etching process, enabling precise control over the opening formation and reducing misalignment issues.
3Area of stationary object
If the capacitor structure is made high and thin to minimize area, then the chip area is reduced, but the contact area between electrode and storage node pad decreases
Solution Approach 1:
The lower electrode structure extends in the vertical dimension to compensate for the reduced horizontal contact area. By forming the lower electrode to extend beyond the opening boundaries, the contact area with the storage node pad is increased in the vertical dimension, maintaining reliability while preserving chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the precision of capacitor formation, reduces misalignment issues, and increases the contact area between the electrode and storage node pad, thereby improving the reliability and efficiency of DRAM capacitor fabrication.
Implementation Method 1
A first etching process is performed to etch through the lattice layer and the template layer, and a portion of the dielectric layer is etched to form a first opening. A second etching process is performed to etch the dielectric layer through the first opening to form a second opening exposing a portion of the top surface of the storage node pad.
Data Source
AI summary
A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.