Capacitor and Register Structures for Semiconductor Devices
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Solution Overview
Problem
The existing 3-D nonvolatile memory devices face manufacturing difficulties due to a significant step difference between the cell region and the peripheral circuit region, leading to a high probability of failure and increased production costs.
Innovation Solution
The capacitor and register structures are designed with edge regions and central regions, featuring stepwise patterns of electrode or register layers, sacrificial layers, support plugs, and slits, allowing for reduced step differences and improved integration by alternately stacking dielectric or interlayer insulating layers, and filling with conductive layers after etching sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the cell region and peripheral circuit region are formed with different layer structures (multi-layered vs. single layer), then the functionality of memory cells and peripheral circuits is achieved, but a great step difference occurs between regions leading to manufacturing difficulty and high failure probability
Solution Approach 1:
The peripheral circuit region is divided into edge regions and a central region. The edge regions maintain stepwise patterns for transistor formation, while the central region uses a filled structure for capacitor formation. This segmentation allows different structural approaches in different sub-regions, resolving the contradiction between functional integration and manufacturing precision.
Solution Approach 2:
The capacitor structure is nested within the peripheral circuit region by forming the capacitor body in the central region surrounded by edge regions. The electrode layers and dielectric layers are alternately stacked and embedded within the peripheral circuit structure, allowing simultaneous formation of memory cells and capacitors without great step differences.
2Ease of manufacture
If capacitors and registers are formed with single layer structures in peripheral circuit region, then manufacturing is simpler, but the area occupied is large and integration is reduced
Solution Approach 1:
The capacitor structure transitions from a planar single-layer configuration to a vertical multi-layer configuration with electrode layers and dielectric layers alternately stacked. This dimensional change allows the capacitor to occupy less area while maintaining capacitance value, resolving the contradiction between manufacturing simplicity and area occupation.
Solution Approach 2:
The capacitor structure uses composite construction with alternating conductive electrode layers and insulating dielectric layers. This composite approach enables compact vertical stacking that reduces footprint area while maintaining ease of manufacture through standardized layer formation processes.
3Manufacturing precision
If memory cells and capacitors are formed in separate processes, then each component can be optimized independently, but the manufacturing process becomes complex and production efficiency is reduced
Solution Approach 1:
The formation of memory cells and capacitors is merged into a single integrated manufacturing process. The electrode layers and dielectric layers are alternately stacked in the same process sequence used for forming memory cell structures, allowing simultaneous formation of both components. This merging maintains manufacturing precision through consistent process parameters while significantly improving production efficiency by eliminating separate processing steps.
Data Source
AI summary
A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.