Capacitor Structure with Sawtooth Liner for Semiconductor Fabrication

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Solution Overview

Problem

The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, making it hard to maintain production efficiency and lower costs.

Innovation Solution

A process for forming a semiconductor device structure involves a series of deposition and etching steps, including the formation of conductive and dielectric layers, a sawtooth-shaped liner layer, and a capacitor structure that enhances capacitance by conformally covering inner walls and bottom surfaces, allowing for simplified manufacturing and increased design flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If feature sizes continue to decrease to increase functional density, then production efficiency improves and costs lower, but fabrication process complexity and difficulty increase

Engineering Contradiction:
Improveproduction efficiencyVSAvoidfabrication process complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The capacitor structure is divided into multiple segments including a bottom electrode, dielectric layer, and top electrode formed through separate deposition and etching steps. This segmentation allows each component to be optimized independently while maintaining overall functionality at reduced feature sizes

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The capacitor design transitions from planar to three-dimensional structures with vertical stacking of electrodes and dielectric layers. This dimensional change increases capacitance density without proportionally increasing lateral feature size, thereby maintaining fabrication feasibility

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If feature sizes continue to decrease to increase functional density, then chip area utilization improves, but manufacturing reliability deteriorates

Engineering Contradiction:
Improvechip area utilizationVSAvoidmanufacturing reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The capacitor structure embeds the dielectric layer within electrodes, and the entire capacitor assembly is integrated within the semiconductor device architecture. This nesting maximizes space utilization while maintaining adequate process margins for reliable fabrication

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The invention adjusts material parameters such as dielectric constant and electrode conductivity to compensate for reduced feature sizes. By changing these parameters, the capacitor maintains required performance levels even as dimensional scaling reduces manufacturing tolerances

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This process simplifies the manufacturing process, reduces costs, and increases capacitance by forming a capacitor structure that efficiently covers and connects conductive elements within the semiconductor device, addressing the challenges of smaller feature sizes and complexity in semiconductor device fabrication.

Implementation Method 1

a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure. The capacitor is electrically connected to the conductive structure.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS9997520B2Semiconductor device structure with capacitor and method for forming the same
Publication Date: 2018.06.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9997520B2 patent drawing
  • US9997520B2 patent drawing
  • US9997520B2 patent drawing

AI summary

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure in or over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the conductive structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The second dielectric layer has a second opening connected to the first opening and exposing the conductive structure. The semiconductor device structure includes a capacitor covering a first inner wall of the first opening, a second inner wall of the second opening, and a top surface of the conductive structure. The capacitor is electrically connected to the conductive structure.