Multilayer Capacitor Side Margins for Crack-Free Sintering
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Solution Overview
Problem
Multilayer ceramic capacitors face issues with delamination and cracks at the junction interface of the side margin portion during sintering, compromising reliability due to differences in shrinkage behavior between the side margin portion and the body, which occurs when maximizing electrode area without a margin.
Innovation Solution
The multilayer electronic component incorporates side margin portions made of dielectric grains with a specific aspect ratio and distribution to control shrinkage, suppressing delamination and cracks by aligning flake-type powder particles in the xy directions and minimizing stress at the junction interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If internal electrodes are exposed in the width direction to maximize electrode area, then capacitance per unit volume is improved, but stress occurs at the junction interface during sintering causing delamination and cracks
Solution Approach 1:
The patent applies local quality by using flake-type powder particles specifically in the side margin portion rather than uniformly throughout the entire component. This creates a localized region with different shrinkage characteristics that matches the body portion, preventing stress concentration at the junction interface while maintaining the electrode exposure design for high capacitance.
Solution Approach 2:
The patent changes the particle shape parameter from spherical to flake-type with specific aspect ratios (length-to-thickness ratio of 2:1 to 10:1). This parameter change fundamentally alters the shrinkage behavior of the side margin portion, enabling it to contract uniformly with the body during sintering and eliminate the stress that causes delamination and cracks.
2Area of stationary object
If side margin portion is separately attached to body before sintering, then electrode area is maximized, but stress occurs at junction interface during sintering
Solution Approach 1:
The patent achieves homogeneity in shrinkage behavior between the side margin portion and the body by using flake-type powder particles with controlled aspect ratios. This ensures that both portions contract at similar rates during sintering, eliminating the stress differential that would otherwise cause delamination and cracks at the junction interface.
3Reliability
If flake-type powder particles are used in side margin portion, then shrinkage is controlled and delamination is suppressed, but manufacturing complexity increases
Solution Approach 1:
The patent segments the ceramic component into two distinct portions: the body portion and the side margin portion. Each portion uses differently shaped powder particles (spherical in body, flake-type in side margin), allowing independent optimization of shrinkage characteristics for each region while maintaining overall structural integrity and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the multilayer ceramic capacitors by preventing delamination and cracks, ensuring uniform shrinkage and maintaining high capacitance per unit volume.
Implementation Method 1
a method of exposing internal electrodes in a width direction of a body in manufacturing a multilayer ceramic capacitor, thereby maximizing an area of the internal electrodes in the width direction through a design without a margin, and separately attaching a ceramic green sheet for a side margin portion to an electrode exposure surface of the body in the width direction before a process of sintering after the body is manufactured, and then performing sintering is applied
Implementation Method 2
stress may occur in a junction interface of the side margin portion and the body during sintering to cause delamination, cracks, etc
Data Source
AI summary
A multilayer electronic component includes a body including a dielectric layer and first and second internal electrodes disposed with the dielectric layer interposed therebetween in a first direction, first and second side margin portions respectively disposed on surfaces of the body in a third direction, and external electrodes respectively disposed on surfaces of the body in a second direction. The first side margin portion includes first dielectric grains, the dielectric layer includes second dielectric grains, and in cross-sections of the first side margin portion and the body in the first and third directions, a ratio of a major axis length to a minor axis length of the first dielectric grain is 3 or greater and 30 or less, and a ratio of a major axis length to a minor axis length of the second dielectric grain is 1.5 or less.


